This section includes guidelines and additional information to facilitate designing with the core.
The aud_clk_out is the audio sampling
clock signal recovered from the reference clock. This signal is of very low frequency
and is used to generate aud_mclk. Hence, an external
PLL is always required to generate the aud_mclk in MHz
range.
The following equation explains how an aud_clk_out is
generated for HDMI:
Aud_clk_out = (Fref * N/(2*CTS)) * (1/OutputDivider)
Fref = RX TMDS Clock frequency
The following equation explains how an aud_clk_out is
generated for DisplayPort:
Aud_clk_out = (Fref * Maud/(2*Naud)) * (1/OutputDivider)
Fref = rxoutclk frequency