IP Facts - 1.0 English

Audio Clock Recovery Unit LogiCORE IP Product Guide (PG335)

Document ID
Release Date
1.0 English
LogiCORE™ IP Facts Table
Core Specifics
Supported Device Family 1 UltraScale+™ , UltraScale™ , Zynq®-7000 SoC, Zynq® UltraScale+™ MPSoC, and 7 series FPGAs
Supported User Interfaces AXI4-Lite
Resources Performance and Resource Use web page
Provided with Core
Design Files Encrypted RTL
Example Design System Verilog
Test Bench System Verilog
Constraints File XDC file delivered with IP generation
Simulation Model Encrypted RTL
Supported S/W Driver N/A
Tested Design Flows 2
Design Entry Vivado® Design Suite
Simulation For supported simulators, see the Xilinx Design Tools: Release Notes Guide.
Synthesis Not Provided
Provided by Xilinx at the Xilinx Support web page
  1. For a complete list of supported devices, see the Vivado® IP catalog.
  2. For the supported versions of the tools, see the Xilinx Design Tools: Release Notes Guide.