|
Core Specifics |
| Supported Device Family
1
|
UltraScale+™
,
UltraScale™
,
Zynq®-7000 SoC,
Zynq®
UltraScale+™ MPSoC, and 7 series FPGAs |
| Supported User Interfaces |
AXI4-Lite
|
| Resources |
Performance and Resource Use web
page
|
| Provided with
Core
|
| Design Files |
Encrypted RTL |
| Example Design |
System Verilog |
| Test Bench |
System Verilog |
| Constraints File |
XDC file delivered with IP generation |
| Simulation Model |
Encrypted RTL |
| Supported S/W Driver |
N/A |
| Tested Design Flows
2
|
| Design Entry |
Vivado® Design Suite
|
| Simulation |
For supported simulators, see the Xilinx Design Tools: Release Notes
Guide. |
| Synthesis |
Not Provided |
| Support |
| Provided by Xilinx
at the Xilinx Support web page
|
- For a complete list of supported devices, see the
Vivado®
IP catalog.
- For the supported versions of the tools, see
the Xilinx Design Tools: Release Notes Guide.
|