| s_axi_ctrl_aclk |
This is the AXI4-Lite
interface clock. This can be of any frequency. Typically in a system, this clock is
shared with other peripherals. |
| ref_clk |
This is the source clock for audio sampling clock recovery.
This is the output of the vid_phy_controller. In case of HDMI it is the TMDS clock
(rx_tmds_clk). In case of DisplayPort, it is the
link clock (rxoutclk). |
| acr_clk |
This is the clock that is used to drive the ACR data from HDMI
or DisplayPort. |
| aud_mclk |
This is the clock generated by the external clock chip. The
frequency of this clock is decided based on the audio peripherals such as DAC/ADC
and/or I2S. This clock is typically an integer multiple of 128*Fs. |
| aud_clk_out |
This is a reference clock signal to be connect to an external
clock chip. This signal is in KHz range and should not be used inside an
FPGA. |
- For more details on clocking and usage,
please refer HDMI and DisplayPort example designs in Designing with the Core.
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