System Interface Ports - 3.0 English

Binary CAM Search v3.0 LogiCORE IP Product Guide (PG317)

Document ID
PG317
Release Date
2024-05-30
Version
3.0 English
Table 1. System Interface
Port Name I/O Clock Description
ram_rstn I ram_clk Asynchronous reset (active-Low). The reset input is synchronized internally to the ram_clk. This port is only present in DUAL_CLOCK mode.
key_rstn I key_clk Asynchronous reset (active-Low). The reset input is synchronized internally to the key_clk.
rst_busy O s_axi_aclk Reset Busy is an active-High indicator that the core is currently in reset state.
sbiterr O key_clk Single-bit error output status. A single-bit error has been detected and corrected by the ECC scrubbing mechanism. The outputs are not triggered by lookup operations, only activated when the ECC scrubber runs every 1 ms.
dbiterr O key_clk Double-bit error output status. A double-bit error has been detected by the ECC scrubbing mechanism. The outputs are not triggered by lookup operations, only activated when the ECC scrubber runs every 1 ms.
debug_status[31:0] O   Debug status port.