Performance - 5.0 English - PG317

Binary CAM Search v5.0 LogiCORE IP Product Guide (PG317)
Document ID
PG317
Release Date
2025-11-26
Version
5.0 English

Maximum Frequencies

The Binary CAM Search IP is designed to run at up to 500 MHz (low voltage)/600 MHz (mid voltage) for -2 speed grade devices.

Latency

The BCAM lookup latency depends on the size of the BCAM the RAM_FREQ / LOOKUP_RATE ratio and the memory type. The lookup latency is constant and some examples are shown in the following table.

Table 1. Lookup Latency
Entries RAM Clock 1x RAM Clock 4x RAM Clock 16x RAM Clock 32x
256 12 14 10 9
972 12 14 10 9
3891 12 14 10 9
15564 12 15 10 9
  1. Latency values are measured in Lookup Interface Frequency cycles.
  2. KEY_WIDTH = 32, RESPONSE_WIDTH = 16, LOOKUP_RATE = LOOKUP_INTERFACE_FREQ = 15M.

Throughput

The lookup throughput corresponds to the LOOKUP_RATE parameter. The highest possible lookup throughput is accomplished when LOOKUP_RATE equals the RAM _FREQ parameter. One Lookup Request can then be issued per RAM clock cycle. The Management Request has strictly lower priority than the Lookup Request, consequently the Management Request throughput becomes:

Management Request Rate = RAM_FREQ - LOOKUP_RATE*TDM_FACTOR

The ECC scrubbing process has the lowest priority. A memory read followed by a potential corrective write is only executed if both the Lookup Request and Management Request FIFOs are empty. Neither the lookup throughput nor the Management Request throughputs are affected. ECC scrubbing of a new address is only initiated if both FIFOs are empty and a potential pending corrective write has been executed.

Management Requests and AXI4-Lite

All Read and Write Management Requests are 64 bits wide. The only exception occurs for insert and update operations of the entry. The insert and update operations write whole entries. Size of a management request is always a multiple of 64 bits. For example, if the entry width is 512 bits then the insert or update operation uses a 512-bit wide management request.

The AXI4-Lite bus uses 13 bits of address and 32 bits of data, so for every Management Request multiple AXI4-Lite writes are issued from the API software. The AXI4-Lite writes are assembled by the secondary AXI4 to a single Management Request. The AXI4-Lite interface is a standard type. Refer to AXI4-Lite IPIF LogiCORE IP Product Guide (PG155).

Note: AXI4-Lite imposes the following requirements when switching between read and write:
  • All outstanding write responses must have been received before issuing a read.
  • All outstanding read responses must have been received before issuing a write.

The following table shows an example calculation for 100 Gb Ethernet rate. Keep in mind the calculated update rate only refers to the hardware resources, the final update rate is most likely limited by the table management software.

Table 2. 100GbE Update Rate Example Calculation (Hardware Limit)
Management Request Size [bits] AXI Lite Write Operations [min / max] Management Update rate

[M updates/s]
64 1 / 3 4.8
128 2 / 5 2.4
256 4 / 9 1.2
512 8 / 17 0.6
1024 16 / 33 0.3
  1. Parameters used in this example: LOOKUP_RATE = 148.8, RAM_FREQ = 600, TDM_FACTOR = 4
  2. The AXI4-Lite maximum number of write operations applies for random data patterns. Minimum number of operations can be achieved when the write data is constant (for example, initializing to zero).