IP Facts Table - 1.0 English

AXI Sideband Formatter Utility LogiCORE IP Product Guide (PG307)

Document ID
Release Date
1.0 English
LogiCORE IP Facts Table
Core Specifics
Supported Device Family 1

UltraScale+, UltraScale, 7 series and Zynq®-7000 AP SoC

Supported User Interfaces AXI4 and AXI3

Not Applicable

Provided with Core
Design Files SystemVerilog
Example Design N/A
Test Bench N/A
Constraints File N/A
Simulation Model Unencrypted SystemVerilog
Supported S/W Driver N/A
Tested Design Flows 2
Design Entry Vivado® Design Suite
Simulation For supported simulators, see the Xilinx Design Tools: Release Notes Guide.
Synthesis Vivado
Provided by Xilinx® at the Xilinx Support web page
  1. For a complete list of supported devices, see the Vivado IP catalog.
  2. For the supported versions of the tools, see the Xilinx Design Tools: Release Notes Guide.