Generating Parity - 1.0 English

AXI Sideband Formatter Utility LogiCORE IP Product Guide (PG307)

Document ID
Release Date
1.0 English

When deploying the AXI Sideband Formatter Utility IP core to perform parity operations, its configuration parameters designate whether parity information exists in the wuser/ruser signals on the S_AXI interface and on the M_AXI interface. When one of the interfaces indicates that it carries no parity and the opposite interface indicates that it does carry parity, then parity bits are generated for the out-bound data channel on the interface with parity enabled. For example, if parity is not present (disabled) on SI and enabled on MI, then parity is generated for the MI W-channel and inserted into the m_axi_wuser output signal, and vice-versa for read parity.

As data channel transfers propagate through the interconnect topology, information contained in the wuser or ruser signal, including parity, remain associated with the corresponding bytes of data at all times. For example, if the interconnect performs a data-width conversion along the AXI pathway, the parity bits associated with the data bytes in each data-beat of the burst, before and after the conversion, remain in the same data-beat as the associated data, and in the correct order. That is why the dimensions of the wuser and ruser signals are always expressed as an integer number of user-bits per byte of data.

For each W-channel or R-channel transfer, parity is generated per byte of data and transmitted in the lowest-order bit-per-byte position of the out-bound wuser or ruser. When generating parity, any in-bound user signal value is left-shifted 1 bit-per-byte (parity bits are interleaved among other byte-related payload). Parity is generated according to the polarity (ODD or EVEN) specified in the configuration parameters.

Parity is generated for all write data byte positions regardless of whether the corresponding wstrb bit is asserted, so that the result can never be misinterpreted as a parity violation.