The following table shows the relationship between the fields in the Vivado IDE and the user parameters (which can be viewed in the Tcl Console).
Model Parameter | Format/Range | Default | Description |
---|---|---|---|
SMID_MODE | string={BYPASS,INSERT,EXTRACT,REMOVE} | BYPASS |
BYPASS: No SMID handling. Any in-bound awuser/aruser info is passed through unchanged. INSERT: The value of SMID_VALUE is inserted into the low-order position of {aw,ar}user; any in-bound value is left-shifted. EXTRACT: The SMID field is extracted from the low-order position of {aw,ar}user and propagated as the out-bound {aw,ar}id (and wid if AXI3). REMOVE: The SMID field is extracted from the low-order position of {aw,ar}user and discarded; the remainder (if any) is right-shifted and propagated |
SMID_VALUE | bitstring(width=SMID_WIDTH) | 6'b0 | The value to be inserted into the low-order position of {aw,ar}user. |
SMID_WIDTH | integer={0..32} | 6 | Width of SMID field. |
MI_PARITY |
string={NONE, ODD, EVEN} |
NONE |
If EVEN or ODD, parity is generated or propagated per byte of write data and is output in the lowest-order bit-per-byte position of the out-bound m_axi_wuser. If SI_PARITY==NONE, parity is generated and inserted, any in-bound value from s_axi_wuser is left-shifted 1 bit-per-byte. If SI_PARITY is the same as MI_PARITY (EVEN or ODD), in-bound parity is propagated as-is (including any parity mismatches). If SI_PARITY is the opposite polarity to MI_PARITY, in-bound parity is inverted and propagated (including any parity mismatches). If EVEN or ODD, parity is expected in the lowest-order bit-per-byte position of the in-bound m_axi_ruser and compared against the corresponding read data byte for parity violation errors. If NONE, any parity received on the SI W-channel is stripped from the lowest-order bit-per-byte position of the out-bound m_axi_wuser, and any remaining value is right-shifted 1 bit-per-byte. If NONE, no parity is expected in the in-bound R-channel. |
SI_PARITY |
string={NONE, ODD, EVEN} |
NONE |
If EVEN or ODD, parity is generated or propagated per byte of read data and is output in the lowest-order bit-per-byte position of the out-bound s_axi_ruser. If MI_PARITY==NONE, parity is generated and inserted, any in-bound value from m_axi_rwuser is left-shifted 1 bit-per-byte. If MI_PARITY is the same as SI_PARITY (EVEN or ODD), in-bound parity is propagated as-is (including any parity mismatches). If MI_PARITY is the opposite polarity to SI_PARITY, in-bound parity is inverted and propagated (including any parity mismatches). If EVEN or ODD, parity is expected in the lowest-order bit-per-byte position of the in-bound s_axi_wuser and compared against the corresponding write data byte for parity violation errors. If NONE, any parity received on the MI R-channel is stripped from the lowest-order bit-per-byte position of the out-bound s_axi_ruser, and any remaining value is right-shifted 1 bit-per-byte. If NONE, no parity is expected in the in-bound W-channel. If SI_PARITY==NONE and MI_PARITY==NONE, then all parity functions are disabled and any {w,r}user signals are propagated as-is. |
S_{AW,AR,B}USER_WIDTH | 0<=integer<=512 | 0 | Width of s_axi_{ar,aw,b}user. |
S_{R,W}USER_BITS_PER_BYTE | 0<=integer<=4 | 0 | Bits-per-byte ratio of s_axi_{w,r}user. |
ADDR_WIDTH | 1<=integer<= 64 | 32 | Width of *_axi_{ar,aw}addr. |
S_ID_WIDTH | 0<=integer<= 32 | 0 | Width of s_axi_{ar,aw,w,r,b}id. |
DATA_WIDTH | integer=2**{5..10} | 32 | Width of *_axi_{r,w}data in bits. |
PROTOCOL | string={AXI4,AXI3} | AXI4 | Protocol of SI and MI interfaces |
READ_WRITE_MODE | string={READ_WRITE,READ_ONLY,WRITE_ONLY} | READ_WRITE | Channel enablement |
ENABLE_PIPELINING _PARITY | Bitstring, width=4 bits | "0010" |
Adds 1 cycle latency between parity error detection and error output for each enabled bit (0-4 latency cycles). Adding pipelining can help timing closure. Bit 0 (LSB): Register the data input from the AXI interface (for error detection only). Bit 1: Pipeline the intermediate parity results for each byte of data (enabled by default). Bit 2: Insert a pipeline stage mid-way between byte-wise parity results and the error output. Bit 3: Register the error output. |
ENABLE_PIPELINING_SMID | Bitstring, width=1 bit | "1" | When SMID_MODE=EXTRACT, incur 1 cycle of latency for the propagation from SI to MI for the AR and AW channels to improve timing (enabled by default). |