Slave Interface Signals

The following table lists the signals associated with each slave interface. If the number of interfaces is configurable, then the signals in Table: Signals Associated with the Slave Interface are replicated for each port. The nn denoted for the signals starts at 00 and increments by one up to 15 for each slave interface instantiated. For IPs that contain only one slave interface the nn value is dropped. For example, the Snn_AXIS_TVALID would be S_AXIS_TVALID . IP cores that do not support multiple clocks do not have the Snn_AXIS_ACLK , Snn_AXIS_ARESETN , or the Snn_AXIS_ACLKEN signals.

Table 2-5: Signals Associated with the Slave Interface
Signal	Direction	Description
snn_axis_aclk	Input	Clock signal. All inputs/outputs of this bus interface are rising edge aligned with this clock.
snn_axis_aresetn	Input	Active-Low synchronous reset signal (all cores, except AXI4-Stream Data FIFO.) Active-Low asynchronous reset signal (AXI4-Stream Data FIFO only.)
snn_axis_aclken	Input	Clock enable signal
snn_axis_tvalid ⁽¹⁾	Input	TVALID indicates that the master is driving a valid transfer. A transfer takes place when both TVALID and TREADY are asserted.
snn_axis_tready ⁽¹⁾	Output	TREADY indicates that the slave can accept a transfer in the current cycle.
snn_axis_tdata [(C_MNN_AXIS_TDATA_WIDTH-1):0] ⁽¹⁾	Input	TDATA is the primary payload that is used to provide the data that is passing across the interface. The width of the data payload is an integer number of bytes.
snn_axis_tstrb [((C_MNN_AXIS_TDATA_WIDTH/8)-1):0] ⁽¹⁾	Input	TSTRB is the byte qualifier that indicates whether the content of the associated byte of TDATA is processed as a data byte or a position byte.
snn_axis_tkeep [((C_MNN_AXIS_TDATA_WIDTH/8)-1):0] ⁽¹⁾	Input	TKEEP is the byte qualifier that indicates whether the content of the associated byte of TDATA is processed as part of the data stream. Associated bytes that have the TKEEP byte qualifier deasserted are null bytes and can be removed from the data stream.
snn_axis_tlast ⁽¹⁾	Input	TLAST indicates the boundary of a packet.
snn_axis_tid [C_NATIVE_TID_WIDTH-1:0] ⁽¹⁾	Input	TID is the data stream identifier that indicates different streams of data.
snn_axis_tdest [(C_NATIVE_TDATA_WIDTH-1):0] ⁽¹⁾	Input	TDEST provides routing information for the data stream.
snn_axis_tuser [(C_SNN_AXIS_TUSER_WIDTH-1):0] ⁽¹⁾	Input	TUSER is user-defined sideband information that can be transmitted alongside the data stream.
s_req_suppress[C_NUM_SI_SLOTS-1:0]	Input	AXI4-Stream Switch only signal. Active-High signal to skip this bus on the next arbitration cycle. While the signal is asserted, this bus does not receive the next arbitration. If this bus already has arbitration granted, it remains granted until the arbitration cycle is completely normally.
s_decode_err[C_NUM_SI_SLOTS-1:0]	Output	AXI4-Stream Switch only signal. One-hot output indicates that a incoming transfer has a TDEST value that not map to a valid Master Interface. Invalid TDEST transfers are dropped. Only valid if the TDEST signal is present and used for routing.
transfer_dropped	Output	AXI4-Stream Subset Converter only signal. This signal is only present if the Slave Interface TREADY signal is not enabled and the Master interface TREADY signal is enabled. This signal indicates if there is an AXI-S transfer that has been dropped due to a de-asserted MI TREADY.
sparse_tkeep_removed	Output	AXI4-Stream Subset Converter only signal. This signal is only present if the Slave Interface TKEEP is enabled and the Master Interface TKEEP is not enabled. This signal signals if there is a Slave Interface TKEEP that has been removed and null data bytes were present.
s_cmd_err[(C_NUM_SI_SLOTS*3)-1:0]	Output	AXI4-Stream Combiner only. This output is not defined and may change in the future.
axis_wr_data_count[31:0]	Output	AXI4-Stream Data FIFO Only. Indicates the write count inside the DATA FIFO. This signal can be used when using asynchronous clocking and can be sampled on the posedge of the s_axis_aclk.
almost_full	Output	Almost Full: When asserted, this signal indicates that only one more write can be performed before the FIFO is full. Not available when Packet Mode is used.
prog_full	Output	Programmable Full: This signal is asserted when the number of words in the FIFO is greater than or equal to the programmable full threshold value. It is de-asserted when the number of words in the FIFO is less than the programmable full threshold value.
injectsbiterr	Input	Single Bit Error Injection- Injects a single bit error if the ECC feature is used. The signal should be asserted with TVALID and can only transition with a TVALID/TREADY handshake.
injectdbiterr	Input	Double Bit Error Injection- Injects a double bit error if the ECC feature is used. Signal should be asserted with TVALID and can only transition with a TVALID/TREADY handshake.
Notes: 1. This signal description is taken from the Arm AMBA Protocol Specification.

Slave Interface Signals - 3.0 English

AXI4-Stream Infrastructure IP Suite (PG085)