Performance - 3.0 English

AXI4-Stream Infrastructure IP Suite (PG085)

Document ID
PG085
Release Date
2023-05-24
Version
3.0 English

The performance of an AXI4-Stream Infrastructure IP core is limited only by the FPGA logic speed. Each core utilizes only block RAMs, LUTs, and registers and contains no I/O elements. The values presented in this section should be used as an estimation guideline, actual performance can vary.