Overview - 3.0 English

AXI4-Stream Infrastructure IP Suite (PG085)

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3.0 English

The Arm® AMBA® 4 Specification builds on the AMBA 3 specifications by adding new interface protocols to provide greater interface flexibility in designs with open standards. Among the new interface protocols is the AXI4-Stream interface which is designed to support low resource, high bandwidth unidirectional data transfers. It is well-suited for FPGA implementation because the transfer protocol allows for high frequency versus clock latency trade-offs to help meet design goals.

The AXI4-Stream protocol is derived from the single AXI3 write channel. It has no corresponding address or response channel and is capable of non-deterministic burst transactions (undefined length). The protocol interface signal set adds optional signals to support data routing, end-of-transaction indicators, and null-beat modifiers to facilitate management and movement of data across a system. These characteristics are suitable for transferring large amounts of data efficiently while keeping gate count low.

The protocol interface consists of a master interface and a slave interface. The two interfaces are symmetric and point-to-point, such that master interface output signals can connect directly to the slave interface input signals. Utilizing this concept, it is possible to design AXI4-Stream modules that have a slave interface input channel and a master interface output channel. Because the master and slave interfaces are symmetric, any number of these modules can be daisy-chained together by connecting the master interface output channel of one module to the slave interface input channel of another module and so on. The function of the modules can be a multitude of different options such as buffering, data transforming or routing.

The AXI4-Stream Infrastructure IP Suite is a powerful collection of modules that provides a rich set of functions for connecting together AXI4-Stream masters and slaves. The IP core is capable of performing data switching/routing, data width conversion, pipelining, clock conversion and data buffering. Parameters and IP configuration Graphical User Interfaces (GUIs) are used to configure the core to suit each of the system designer's requirements.