Global Signals - 3.0 English

AXI4-Stream Infrastructure IP Suite (PG085)

Document ID
PG085
Release Date
2023-05-24
Version
3.0 English

These signals are always present when there is a common clock between all interfaces of the IP core.

Table 2-4: Global Signals

Signal

Direction

Description

aclk

Input

Global Clock Signal. Drives the clocks on the AXI4-Stream Switch and is the primary clock to the system.

aresetn

Input

Global Reset Signal. This active-Low signal drives the reset pins on the AXI4-Stream Switch and is the primary reset of the system.

aclken

Input

Global ACLK Enable signals. Drives the ACLKEN pins on the AXI4-Stream Switch and is the primary ACLKEN of the system.

aclk2x

Input

This auxiliary clock input is only enabled on the AXI4-Stream Register Slice when configured in SLR TDM Crossing mode, and must be exactly twice the frequency of aclk and generated from the same clock source with zero phase shift.