The input and output clock frequencies are 100 MHz in the Clocking Wizard by default.
1. The output clock frequency needs to be reconfigured to 50 MHz with a phase shift of 90°, as shown below:
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X-Ref Target - Figure 4-18 
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2. The table in the DRP Registers tab gets updated for the user requirements on the clock, as shown below:
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X-Ref Target - Figure 4-19 
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3. The table specifies all the AXI registers with the address and the data which needs to be written into it. Configure all the AXI Registers with respect to the table.
4. Configure Clock Configuration Register 24 (Address: C_BASEADDR + 0x35C) with 0x00000003 to set the LOAD and SEN bits.
5. Wait for the locked signal. The new frequency can be checked at the clkout1 output port.
IMPORTANT: When Dynamic Reconfiguration is selected using the DRP interface, refer to MMCM and PLL Dynamic Reconfiguration (XAPP888) [Ref 6] for the steps to reconfigure the clocking primitive. You can use the MMCM register details to configure different M and D values.