Clock |
Frequency (MHz) |
Duty Cycle |
---|---|---|
clk_out2 |
300 (= clk_out1/2) |
50 |
1. Optimize clock structure not enabled:
° The resource tab shows one PLL, one IBUFG, and two BUFGs.
° The summary table is updated as follows:
X-Ref Target - Figure 3-7 |
° The clocking structure is as follows:
X-Ref Target - Figure 3-8 |
2. Optimize clock structure enabled:
° The resource tab shows one PLL, one IBUFG, one BUFG, and one BUFGCE_DIV.
° The summary table is updated as follows:
X-Ref Target - Figure 3-9 |
° The clocking structure is as follows:
X-Ref Target - Figure 3-10 |