The Clock Monitor error status register, the Interrupt status register, and the Interrupt enable register have the following bit map:
|
Bit Number |
Description |
|---|---|
|
0 |
User clock 0 frequency is greater than the specifications. |
|
1 |
User clock 1 frequency is greater than the specifications. |
|
2 |
User clock 2 frequency is greater than the specifications. |
|
3 |
User clock 3 frequency is greater than the specifications. |
|
4 |
User clock 0 frequency is lesser than the specifications. |
|
5 |
User clock 1 frequency is lesser than the specifications. |
|
6 |
User clock 2 frequency is lesser than the specifications. |
|
7 |
User clock 3 frequency is lesser than the specifications. |
|
8 |
Glitch occurred in user clock 0. |
|
9 |
Glitch occurred in user clock 1. |
|
10 |
Glitch occurred in user clock 2. |
|
11 |
Glitch occurred in user clock 3. |
|
12 |
Clock stop on user clock 0. |
|
13 |
Clock stop on user clock 1. |
|
14 |
Clock stop on user clock 2. |
|
15 |
Clock stop on user clock 3. |
|
16-31 |
Undefined. |