The Timing Constraints wizard recommends generated clock constraints on output ports that are driven by double data-rate registers with constant inputs. Based on the input constant connectivity, the generated clock phase is adjusted to either positive (0 degree phase shift) or inverted (180 degree phase shift). The master clock used in the constraint is the clock that reaches the clock pin of the double data-rate register. See the Source Clock column of the Recommended Constraints table in the following figure:
For the 7 series device family, the topology recognized by the wizard is shown in the following figure. There is no restriction on the nature of the master clock or the output buffer.
For the UltraScale device family, the ODDR and ODDRE1 primitives are automatically retargeted to OSERDESE3 with the property ODDR_MODE=TRUE. The wizard recognizes the topology shown in the following figure, where OSERDESE3/D[0] is connected to 1 and OSERDESE3/D[4] is connected to 0 (no phase-shift).
