Synthesis and Implementation Constraint Files

Synthesis and Implementation Constraint Files - 2023.1 English

Vivado Design Suite User Guide: Using Constraints (UG903)

Document ID

UG903

Release Date

2023-05-16

Version

2023.1 English

By default, all XDC files and Tcl scripts added to a constraint set are used for both synthesis and implementation. Set the USED_IN_SYNTHESIS and USED_IN_IMPLEMENTATION properties on the XDC file or the Tcl script to change this behavior. This property can take the value of either TRUE or FALSE.

Important: The DONT_TOUCH attribute does not obey the properties of USED_IN_SYNTHESIS and USED_IN_IMPLEMENTATION. If you use DONT_TOUCH properties in the synthesis XDC, it is propagated to implementation regardless of the value of USED_IN_IMPLEMENTATION. For more information about the DONT_TOUCH attribute, refer to RTL Attributes.

Important: If any module (IP/BD/...) is synthesized in Out-Of-Context (OOC) mode, the top-level synthesis run infers a black box for these modules. Hence, the top-level synthesis constraints will not be able to reference objects such as pins, nets, cells, etc., that are internal to the OOC module. If some top-level constraints refer to objects inside any OOC module, you may need to split the constraints into two files: one XDC file for Synthesis (USED_IN_SYNTHESIS=TRUE / USED_IN_IMPLEMENTATION=FALSE) and one XDC file for implementation (USED_IN_SYNTHESIS=FALSE / USED_IN_IMPLEMENTATION=TRUE). There is no such limitation during implementation since the netlists from the OOC module DCPs are linked with the netlist produced when synthesizing the top-level design files, and the Vivado Design Suite resolves the black boxes. The XDC output products that were generated for use during implementation are applied along with any user constraints.

For example, to use a constraint file for implementation only:

Select the constraint file in the Sources window.
In the Source File Properties window:
1. Uncheck Synthesis.
2. Check Implementation.

The equivalent Tcl commands are:

set_property USED_IN_SYNTHESIS false [get_files wave_gen_pins.xdc]
set_property USED_IN_IMPLEMENTATION true [get_files wave_gen_pins.xdc]

When running Vivado in Non-Project Mode, you can read in the constraints directly between any steps of the flow. The properties USED_IN_SYNTHESIS and USED_IN_IMPLEMENTATION do not matter in this mode.

The following compilation Tcl script shows how to read two XDC files for different steps of the flow:

read_verilog [glob src/*.v] 
read_xdc wave_gen_timing.xdc
synth_design -top wave_gen -part xc7k325tffg900-2 
read_xdc wave_gen_pins.xdc
opt_design 
place_design 
route_design

Table 1. Reading XDC Files Before and After Synthesis
File Name	File Placement	Used For
wave_gen_timing.xdc	Before synthesis	Synthesis Implementation
wave_gen_pins.xdc	After synthesis	Implementation

Tip: The constraints read in after synthesis are applied in addition to the constraints read in before synthesis.