Adjusting Constraints for Synthesis Logic Replication - 2023.1 English

During synthesis, some registers are replicated to improve the design performance. The user XDC constraints are not modified by the synthesis engine to include the replicated cells. If a timing constraint is attached to an object replicated by Vivado Synthesis, the replicated cells are not always covered by the XDC constraints depending on how the constraint is written, which can later impact the implementation quality of results.

When using Vivado Synthesis, the get_cells and get_pins commands provide a mechanism to automatically include the replicated objects.

For example, set_false_path –from [get_cells –hierarchical *rx_reg] can be rewritten as follows to also safely include the replicated objects during implementation:

set_false_path -from [get_cells -hierarchical *rx_reg -include_replicated_objects]

The command line option -include_replicated_objects relies on the property ORIG_CELL_NAME set on the replicated objects. The following query commands return the original cells with the replicated cells:

get_cells -include_replicated_objects *rx_reg
get_cells -include_replicated_objects [get_cells -hier -filter {NAME =~ *rx_reg}] 
get_cells -hierarchical -filter {NAME =~ *rx_reg || ORIG_CELL_NAME =~ *rx_reg}

The -filter option always applies after the collection of objects is built. It is not recommended to use -filter with -include_replicated_objects when the filtering expression refers to the property NAME. In such scenarios, the replicated objects are not returned when they do not match the pattern specified for NAME. For example, the syntax below does not return replicated objects matching *reg_replica*:

get_cells -include_replicated_objects -filter {NAME =~ *rx_reg}

AMD recommends running the Methodology checks (report_methodology) and reviewing the XDCV-1 and XDCV-2 check messages to identify constraints that need to be updated with the get_cells/get_pins -include_replicated_objects option.

Figure 1. Creating Constraints with the Synthesized Design

Before proceeding to implementation, you must verify that your design does not include any major timing violation. The place-and-route tools can fix most reasonable timing violations, but they cannot fix fundamental design issues that make timing closure impossible.

For more information, see this link in the Vivado Design Suite User Guide: Synthesis (UG901), or this link in the Vivado Design Suite User Guide: Implementation (UG904).