In this stage you will generate the graph code of this design and perform bit-true and cycle true simulations with the AI Engine Simulator.
Select the four AIE FIR Filters and the Frequency shifting block and type CTRL+G to group them in a subsystem. Assign a new name: FIRchain.
Click the canvas and type
model co. Set the Subsystem name toFIRchain.Double-click the block Model Composer Hub, select the AI Engine / Settings target and set the following parameters:
Check Create testbench
Check Run cycle approximate AIE Simulation after code generation
Check Plot AIE Simulation Output and Estimate Throughput
Check Collect Data for Vitis Analyzer
Click Apply
Select the Generate tab:
Click on Generate.
The simulink design is run to generate the testbench, then the graph code is generated and compiled. The source code can be viewed in ./code/src_aie/FIRchain.h:
#ifndef __XMC_FIRCHAIN_H__
#define __XMC_FIRCHAIN_H__
#include <adf.h>
#include "./FIR_Halfband_Decimator_b6bb9f39/FIR_Halfband_Decimator_b6bb9f39.h"
#include "./FIR_Halfband_Decimator_c797d059/FIR_Halfband_Decimator_c797d059.h"
#include "./FIR_Halfband_Decimator_714ce49a/FIR_Halfband_Decimator_714ce49a.h"
#include "./FIR_Symmetric_00c44acd/FIR_Symmetric_00c44acd.h"
#include "aiecode_src/FreqShift.h"
class FIRchain_base : public adf::graph {
public:
FIR_Halfband_Decimator_b6bb9f39 FIR_Halfband_Decimator;
FIR_Halfband_Decimator_c797d059 FIR_Halfband_Decimator1;
FIR_Halfband_Decimator_714ce49a FIR_Halfband_Decimator2;
FIR_Symmetric_00c44acd FIR_Symmetric;
adf::kernel FreqShift_0;
public:
adf::input_port In1;
adf::output_port Out1;
FIRchain_base() {
// create kernel FreqShift_0
FreqShift_0 = adf::kernel::create(FreqShift<256>);
adf::source(FreqShift_0) = "aiecode_src/FreqShift.cpp";
// create kernel constraints FreqShift_0
adf::runtime<ratio>( FreqShift_0 ) = 0.9;
// create nets to specify connections
adf::connect< > net0 (In1, FIR_Halfband_Decimator.in);
adf::connect< > net1 (FIR_Halfband_Decimator.out, FIR_Halfband_Decimator1.in);
adf::connect< > net2 (FIR_Halfband_Decimator1.out, FIR_Halfband_Decimator2.in);
adf::connect< > net3 (FIR_Halfband_Decimator2.out, FIR_Symmetric.in);
adf::connect< adf::window<1024> > net4 (FIR_Symmetric.out, FreqShift_0.in[0]);
adf::connect< adf::window<1024> > net5 (FreqShift_0.out[0], Out1);
}
};
class FIRchain : public adf::graph {
public:
FIRchain_base mygraph;
public:
adf::input_plio In1;
adf::output_plio Out1;
FIRchain() {
In1 = adf::input_plio::create("In1",
adf::plio_32_bits,
"./data/input/In1.txt");
Out1 = adf::output_plio::create("Out1",
adf::plio_32_bits,
"Out1.txt");
adf::connect< > (In1.out[0], mygraph.In1);
adf::connect< > (mygraph.Out1, Out1.in[0]);
}
};
#endif // __XMC_FIRCHAIN_H__
Finally, the bit-exact simulation (Emulation-AIE) is performed and the result compared to the Simulink simulation:
Vitis Analyzer is then launched. From here you can see the Graph View, the Array View, the Timeline, and the Profile information.
The Simulation Data Inspector opens-up and we can see the output frames and the estimate of the output throughput as shown below:
Here the estimated throughput is 44 MSPS instead of the expected 100 MSPS. You can use Vitis Analyzer to track the reason of this throughput reduction. Here it is very easy to see that the input stream feeds the data @250 MSPS instead of the 800 MSPS that were expected in the graph. The reason is that the input bitwidth is 32 bits at a rate of 250MHz (default value) as can be seen at the end of the FIRchain.h file.