The vck_190_v1_0_xsa.tcl script then calls the dr.bd.tcl script, which generates the platform block design. Open the block design in the Vivado project located at hw/build/vck190_v1_0_vivado/vck190_v1_0.xpr. You will notice that there are five major components to the hardware platform: the AI Engine, CIPS, NoC (Network-on-Chip), Clocking Wizard IP, Clock Reset IPs, 16 AXI4-LITE SmartConnect interfaces, and a top-level AXI4-Lite SmartConnect (called ctrl_sm).
Open the dr.bd.tcl file and review the comments. After the Setup and Error Checking commands, you will notice that the main function of this file is called create_root_design.