The Array View gives you a logical device view of the AI Engine and how the kernels are placed and how they are connected to each other as well as the shim.
Cross probe to kernel and graph source files
The table at the bottom would show the following:
Kernel - The kernels in the graph.
PL - Shows connections between the graph and PLIO.
Buffer - Will show all the buffers used for inputs/outputs of the graph and the buffers for kernels.
Port - Shows all the ports of each kernels and ADF Graph.
Net - Shows all nets, named and generated, mapped in the ADF Graph.
Tile - Shows tile data (kernels, buffers) of mapped tiles and their grid location.
Tip: To see more detailed information about these tables go to Chapter 9 - Section: “Viewing Compilation Results in the Vitis Analyzer”.
You can zoom into the view to get finer detail of the AI Engine and see how tiles are made up as seen in the following screenshot.
To zoom in, click and drag from the upper-left area you want to view to have a box show up around the area to zoom. Below is a zoomed in area too look at.
In this zoomed in location you can see how the kernels are connected to a variety of tiles and how the shim is connected to the PLIO ports of this design.
Click on Simulator Output.