Out-of-Context Flow - 2022.1 English

Vivado Design Suite User Guide : Designing with IP (UG896)

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2022.1 English

Using the OOC flow when generating IP is recommended and is also the default behavior in the Vivado Design Suite. The OOC flow speeds up run time for the complete project, and lets you avoid re-synthesizing IP when doing project runs.

In the OOC flow, the Vivado tools synthesize the IP as a standalone module and produces an OOC design checkpoint (DCP). The Vivado tools also generate and use a special OOC flow-only, Xilinx design constraint (XDC) output product file, the _ooc.xdc, when synthesizing the IP, which provides default input clock definitions. The produced DCP is a container file, and includes a netlist as well as constraints. The _ooc.xdc file is part of the IP definition.

When synthesizing the top-level design, an HDL stub module is provided with the DCP file, and causes a black box to be inferred for the IP. Also, the DCP provides an XDC file, the _in_context.xdc file, during synthesis of the entire design, which defines any clocks an IP might output, for use by the top-level design. See Managing IP Constraints for more information.

If any IP is synthesized in OOC mode, the top level synthesis run infers a black box for these IP. Hence, users will not be able to reference objects such as pins, nets, cells, etc., that are internal to the IP as part of the top level synthesis constraints.

During implementation, the netlists from the IP DCPs are linked with the netlist produced when synthesizing the top-level design files, and the Vivado Design Suite resolves the IP black boxes. The IP XDC output products that were generated for use during implementation are applied along with any user constraints.

The OOC flow is the default flow because of two main benefits:

  • It improves synthesis run times because you only synthesize the IP when changes to the IP customization or version require it, rather than re-synthesizing it as part of the top-level design.
  • It produces an <ip_name>_sim_netlist.v or an <ip_name>_sim_netlist.vhdl structural simulation netlist. You can use these files during simulation if you use a single language simulator and the IP does not deliver behavioral HDL in that language. See Simulating IP for more information.
    Note: In versions of the Vivado Design Suite that are older than 2015.3, the simulation files are named *_funcsim.v and *_funcsim.vhdl.