This chapter describes the features of Designing with IP.
Note: Where there is a blue link on a Tcl command, you can go directly to the Vivado Design Suite Tcl Command Reference Guide (UG835) for more information about the command. You can also use
<command_name> -help in the Vivado IDE.
Working with Xilinx® IP consists of first customizing an IP for use in an RTL design. You can create an IP customization in various ways using the Vivado® Design Suite, as follows:
- Directly customizing an IP into a project from the IP catalog.
- Using the Manage IP project flow to create a stand-alone customization of an IP for use in the current project as well as others. See Using Manage IP Projects for more information.
- Using a Tcl script to create an IP customization in either Project or Non-Project mode.
- Adding or creating block designs (BDs).
After creating a customization, you can generate output products or defer generation until later.
- In Project mode, if output products are not present, the Vivado tools generate the required output products automatically prior to synthesis or simulation. By default, output products are generated out-of-context (OOC) for synthesis. See Out-of-Context Flow for more information.
- In Non-Project mode, you must generate the output products manually prior to synthesis or simulation.
To use an IP customization in a design you must instantiate the IP in the HDL code of your top-level design. The IP output products have instantiation templates in both VHDL and Verilog that are generated automatically. See Using IP Project Settings for more information.
Video: See the Vivado Design Suite QuickTake Video: Getting Started with Vivado IDE for more information on using Vivado IDE.