To specify the simulator language, type the following command in the Tcl Console:
set_property SIMULATOR_LANGUAGE <language_option>
[current_project]
The following table shows the simulation language properties, language, and simulation model where the property is applied.
| Simulation Model | Language | Simulation Model |
|---|---|---|
| IP delivers VHDL and Verilog behavioral models | Mixed | Behavioral simulation model provided in the specified
SIMULATOR_LANGUAGE. |
| Verilog | Verilog behavioral model. | |
| VHDL | VHDL behavioral model. | |
| IP delivers Verilog behavioral model only | Mixed | Verilog behavioral model. |
| Verilog | Verilog behavioral model. | |
| VHDL | VHDL simulation netlist generated from the IP DCP. | |
| IP delivers VHDL behavioral model only | Mixed | VHDL behavioral model. |
| Verilog | Verilog simulation netlist generated from the IP DCP. | |
| VHDL | VHDL behavioral model. | |
| IP deliver no behavioral models | Mixed/Verilog/VHDL | Structural simulation netlist generated from the DCP in the specified
SIMULATOR_LANGUAGE. |
Note: Where available, a Behavioral Simulation model always takes precedence over a
Structural Simulation netlist. Vivado does not offer a choice of simulation
model.
Note: The setting for the project property SIMULATOR_LANGUAGE is used to determine
the simulation models delivered when the IP supports both Verilog and VHDL.