Scripting Examples - 2022.1 English

Vivado Design Suite User Guide : Designing with IP (UG896)

Document ID
UG896
Release Date
2022-05-19
Version
2022.1 English

Implementing an IP Example Design

Create a project to run implementation on an IP example design.

# Create a project
create_project <name> <dir> -part <part>
# Create an IP customization and a DCP 
# This will also generate all the output products
create_ip ...
create_ip_run [get_ips <ip>.xci]
launch_runs <ip>_synth_1
wait_on_run <ip>_synth_1
# Open the example design for the IP
# This will use the IP DCP generated
open_example_project -force -dir <project_location> -in_process [get_ips <ip>]
launch_runs synth_1
wait_on_run synth_1
launch_runs impl_1
wait_on_run impl_1 -to write_bitstream
open_run impl_1 
# produce some reports
report_timing_summary ...
report_utilization ... 

Non Project Synthesis

When you synthesize and implement a design in a non-project flow, you could have one IP which has an OOC DCP generated and one IP being synthesized along with user logic.

When reading an IP XCI file, all output products that are present, including an OOC DCP, are used, and there is no need to generate these files.

If the output products have not been generated for the IP, you must generate the output products (or create a DCP using the synth_ip command which generates the output products also).

If you elect to use global synthesis for an IP (see the Synthesis Options for IP) then you must disable checkpoint support and generate the output products. The following Tcl script provides a template for this action:

#create an in memory project to provide the part to use for IP creation and for
#running synthesis
set_part <part>
# read in sources 
read_verilog top.v
# Read in an existing IP customization
# or create an IP from scratch
# create_ip ... or read_ip ip1.xci
# Generate a DCP for the IP
# will generate output products if needed
synth_ip [get_ips ip1]
# Read in an existing IP customization
# or create an IP from scratch
# create_ip ... or read_ip ip2.xci
# Set IP to use global synthesis (no DCP generated)
set_property generate_synth_checkpoint false [get_files ip2.xci]
# Need to generate output products for IP 
generate_target all [get_ips ip2]
# synthesis the complete design
synth_design -top top 
# run implementation
opt_design 
place_design 
route_design 
# write the bitstream
write_bitstream -file top 

Simulating an IP Example Design

Create a project to run simulation on an IP example design.

#create the project
create_project <name> <dir> -part <part> 
# create IP and a synthesis run
create_ip ...
create_ip_run [get_ips <ip_name>] 
#launch runs
launch_runs <ip>_synth_1
wait_on_run <ip>_synth_1
#open the example project
open_example_project -force -dir <project_location> -in_process [get_ips <ip>]
#launch simulation
<launch_simulation> | <target_simulator>

Synthesizing and Simulating an IP

If an IP does not deliver an example design, but does deliver a test bench, you can perform simulation of just the IP.

#create the project
create_project <name> <dir> -part <part>
# create_ip ... or add_files ip.xci 
# create an IP design run 
create_ip_run [get_ips <ip_name>] 
#launch IP synthesis run 
launch_run <ip>_synth_1
wait_on_run <ip>_synth_1 
# Setting up simulation test bench
set_property top <tb> [current_fileset -simset] 
# Launch simulation
<launch_simulation> | <target_simulator>