Using the Memory Generator Wizard (for Block Memory) - 2022.1 English

Xilinx Power Estimator User Guide (UG440)

Document ID
Release Date
2022.1 English
In the 7 series/ Zynq®-7000 SoC and later devices XPE spreadsheets, the Memory Generator wizard allows you to enter block memory information in the spreadsheet. You can access the Memory Generator Wizard by clicking the Manage IP button on the Summary sheet or the IP Manager sheet, or the Add Memory button on the Block RAM sheet. The XPE Memory Generator wizard provides a simplified method of filling in the Block RAM sheet in XPE. To populate the Block RAM sheet using the XPE Memory Generator Wizard (example shown below is for 7 series devices):
  1. Open the Memory Generator wizard using one of the following methods:

    On the Logic Sheet, click Add Memory.


    On the IP Manager Sheet, click Manage IP.

    1. In the IP Manager dialog box, click Create IP.
    2. In the dialog box IP catalog, select Block Memory.
    3. In the dialog box, click Create.
  2. In the Block Memory tab of the XPE Memory Generator dialog box, fill out the information in the dialog box for one block memory Memory Type in your design.

    The fields in the Block Memory tab are:

    Memory Type
    Select the type of memory your design will use.
    • Single Port RAM
    • Simple Dual Port RAM
    • Single Port ROM
    • Dual Port ROM
    Enter the clock frequency at which the distributed memory will operate. For dual-port memory types, XPE assumes the same clock frequency for both Port A and Port B.
    Specify which of these algorithms the Xilinx design tools will use to configure block RAM primitives and connect them together:
    Minimum Area
    The memory is generated using the minimum number of block RAM primitives.
    Low Power
    The memory is generated such that the minimum number of block RAM primitives are enabled during a Read or Write operation.
    Enter the average toggle rate of the data signals. A toggle rate of 50% means that half of the data signals toggle each clock cycle.
    Port A and Port B
    If you have selected a single port Memory Type, you will enter information for Port A only. If you have selected a dual port Memory Type, you will enter information for both Port A and Port B.
    Enter the bit width for each word in the port.
    Enter the depth of the port . Width × Depth is the total number of bits in the memory.
    Enter the percentage of time that the port will be enabled.
    Select the operating mode for the block RAM: READ_FIRST, WRITE_FIRST, or NO_CHANGE.
    Module name
    Allows you to assign a name to the generated block memory configuration. This will help to distinguish multiple configurations in the XPE sheets.
  3. When you have filled out the values for this block memory, click Create.

    A row in the Block Ram sheet and a row in the Logic sheet will be filled in with the information you entered in the dialog box.

  4. For each block memory type in your design, fill out the dialog box and click Create.

    Each time you click Create a row is added to the Block RAM sheet and the Logic sheet.

  5. When you have configured all of the block memory in your design, click Close to close the XPE Memory Generator dialog box.

7 Series FPGAs Memory Resources User Guide (UG473) and UltraScale Architecture Memory Resources User Guide (UG573).