Specifying Clocks - 2022.1 English

Xilinx Power Estimator User Guide (UG440)

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2022.1 English

Important factors in dynamic power calculation are the activity and the load capacitance that needs to be switched by each net in the design. Some of the factors in determining the loading capacitance are fanout, wire length, and so forth. With clocks typically having higher activity and fanouts, the power associated with clock nets can be significant and thus is reported in a separate worksheet sheet as shown in the following figure.

For the information needed to fill out the Clock Tree Power sheet, see the 7 Series FPGAs Clocking Resources User Guide (UG472) or the UltraScale Architecture Clocking Resources User Guide (UG572).

Figure 1. Clock Tree Power Sheet (7 Series Devices)
  • Buffer Type Column

    Xilinx® devices have different types of buffers capable of driving the clock routing structures and these types are modeled within XPE.

  • Clock Fanout Column (7 series and UltraScale™ XPE Spreadsheets)

    The number of synchronous elements driven by this clock. The best way to fill in this filed is to sum up the total number of registers, block RAMs and DSPs specified in their respective sheets for a clock.

  • Fanout/Site Column

    Fanout/site column in UltraScale+™ devices represents the average number of connections of the clock to a physical logic in a site such as a CLB, block RAM, or DSP block.

    Figure 2. Fanout/Site for UltraScale+ Devices

    For early power estimation, it is recommended to leave the value as is. For imported .xpe files, the value is provided by the Vivado® tools, and is based on the placed and routed results to improve clock power accuracy. The value ranges from 1 (least efficient, highest power) to 16 (most efficient, lowest power). For block RAM and DSP sites, the value should be 1, as there is only one fanout in these sites.

  • Clock Buffer Enable Column

    Gates the clock net at its source. The value is the percentage of the time in which the clock buffer is active. Reduce this percentage if you plan on disabling the clock net at the source when this portion of the design is not used. This reduces power.

  • Slice Clock Enable Column

    Gates the clock net at its loads at CLB level. Reduce this percentage if you plan on disabling some of the clock loads with slice level Clock Enable signals. This reduces power.

    Note: Some algorithms in software such as Intelligent Clock Gating will remap or change the packing to minimize this number.