Parameterized Macro: Synchronizer via Gray Encoding
- MACRO_GROUP: XPM
- MACRO_SUBGROUP: XPM_CDC
Introduction
This macro synchronizes a binary input from the source clock domain to the destination clock domain using gray code. For proper operation, the input data must be sampled two or more times by the destination clock.
This module takes the input binary signal, translates it into Gray code and registers it, synchronizes it to the destination clock domain, and then translates it back to a binary signal. You can define the number of register stages used in the synchronizers. You can also enable a simulation feature to generate messages to report any potential misuse of the macro.
Because this macro uses Gray encoding, the binary value provided to the macro must only increment or decrement by one to ensure that the signal being synchronized has two successive values that only differ by one bit. This will ensure lossless synchronization of a Gray coded bus. If the behavior of the binary value is not compatible to Gray encoding, use the XPM_CDC_HANDSHAKE macro or an alternate method of synchronizing the data to the destination clock domain.
report_cdc
is run, the synchronizer in
this module is reported as a warning of type CDC-6, Multi-bit synchronized with
ASYNC_REG property. This warning is safe to ignore because the bus that is
synchronized is gray-coded. Starting in 2018.3, this warning has been suppressed
by adding a CDC-6 waiver to the Tcl constraint file.You should run report_cdc
to make sure the CDC structure is identified and that
no critical warnings are generated, and also verify that dest_clk
can sample src_in_bin[n:0]
two or more times.
Port Descriptions
Port | Direction | Width | Domain | Sense | Handling if Unused | Function |
---|---|---|---|---|---|---|
dest_clk | Input | 1 | NA | EDGE_RISING | Active | Destination clock. |
dest_out_bin | Output | WIDTH | dest_clk | NA | Active | Binary input bus (src_in_bin) synchronized to destination clock domain. This output is combinatorial unless REG_OUTPUT is set to 1. |
src_clk | Input | 1 | NA | EDGE_RISING | Active | Source clock. |
src_in_bin | Input | WIDTH | src_clk | NA | Active | Binary input bus that will be synchronized to the destination clock domain. |
Design Entry Method
Instantiation | Yes |
Inference | No |
IP and IP Integrator Catalog | No |
Available Attributes
Attribute | Type | Allowed Values | Default | Description |
---|---|---|---|---|
DEST_SYNC_FF | DECIMAL | 2 to 10 | 4 | Number of register stages used to synchronize signal in the destination clock domain. |
INIT_SYNC_FF | DECIMAL | 0, 1 | 0 |
0- Disable behavioral simulation initialization value(s) on synchronization registers. 1- Enable behavioral simulation initialization value(s) on synchronization registers. |
REG_OUTPUT | DECIMAL | 0, 1 | 0 |
0- Disable registered output 1- Enable registered output |
SIM_ASSERT_CHK | DECIMAL | 0, 1 | 0 |
0- Disable simulation message reporting. Messages related to potential misuse will not be reported. 1- Enable simulation message reporting. Messages related to potential misuse will be reported. |
SIM_LOSSLESS_GRAY_CHK | DECIMAL | 0, 1 | 0 |
0- Disable simulation message that reports whether src_in_bin is incrementing or decrementing by one, guaranteeing lossless synchronization of a gray coded bus. 1- Enable simulation message that reports whether src_in_bin is incrementing or decrementing by one, guaranteeing lossless synchronization of a gray coded bus. |
WIDTH | DECIMAL | 2 to 32 | 2 | Width of binary input bus that will be synchronized to destination clock domain. |
VHDL Instantiation Template
Library xpm;
use xpm.vcomponents.all;
-- xpm_cdc_gray: Synchronizer via Gray Encoding
-- Xilinx Parameterized Macro, version 2022.1
xpm_cdc_gray_inst : xpm_cdc_gray
generic map (
DEST_SYNC_FF => 4, -- DECIMAL; range: 2-10
INIT_SYNC_FF => 0, -- DECIMAL; 0=disable simulation init values, 1=enable simulation init values
REG_OUTPUT => 0, -- DECIMAL; 0=disable registered output, 1=enable registered output
SIM_ASSERT_CHK => 0, -- DECIMAL; 0=disable simulation messages, 1=enable simulation messages
SIM_LOSSLESS_GRAY_CHK => 0, -- DECIMAL; 0=disable lossless check, 1=enable lossless check
WIDTH => 2 -- DECIMAL; range: 2-32
)
port map (
dest_out_bin => dest_out_bin, -- WIDTH-bit output: Binary input bus (src_in_bin) synchronized to
-- destination clock domain. This output is combinatorial unless REG_OUTPUT
-- is set to 1.
dest_clk => dest_clk, -- 1-bit input: Destination clock.
src_clk => src_clk, -- 1-bit input: Source clock.
src_in_bin => src_in_bin -- WIDTH-bit input: Binary input bus that will be synchronized to the
-- destination clock domain.
);
-- End of xpm_cdc_gray_inst instantiation
Verilog Instantiation Template
// xpm_cdc_gray: Synchronizer via Gray Encoding
// Xilinx Parameterized Macro, version 2022.1
xpm_cdc_gray #(
.DEST_SYNC_FF(4), // DECIMAL; range: 2-10
.INIT_SYNC_FF(0), // DECIMAL; 0=disable simulation init values, 1=enable simulation init values
.REG_OUTPUT(0), // DECIMAL; 0=disable registered output, 1=enable registered output
.SIM_ASSERT_CHK(0), // DECIMAL; 0=disable simulation messages, 1=enable simulation messages
.SIM_LOSSLESS_GRAY_CHK(0), // DECIMAL; 0=disable lossless check, 1=enable lossless check
.WIDTH(2) // DECIMAL; range: 2-32
)
xpm_cdc_gray_inst (
.dest_out_bin(dest_out_bin), // WIDTH-bit output: Binary input bus (src_in_bin) synchronized to
// destination clock domain. This output is combinatorial unless REG_OUTPUT
// is set to 1.
.dest_clk(dest_clk), // 1-bit input: Destination clock.
.src_clk(src_clk), // 1-bit input: Source clock.
.src_in_bin(src_in_bin) // WIDTH-bit input: Binary input bus that will be synchronized to the
// destination clock domain.
);
// End of xpm_cdc_gray_inst instantiation