Parameterized Macro: Asynchronous Reset Synchronizer
- MACRO_GROUP: XPM
- MACRO_SUBGROUP: XPM_CDC
Introduction
This macro synchronizes an asynchronous reset signal to the destination clock domain. The resulting reset output will be guaranteed to assert asynchronously in relation to the input but the deassertion of the output will always be synchronous to the destination clock domain.
You can define the polarity of the reset signal and the minimal output pulse width of the macro when asserted. The latter is controlled by defining the number of register stages used in the synchronizers.
Port Descriptions
Port | Direction | Width | Domain | Sense | Handling if Unused | Function |
---|---|---|---|---|---|---|
dest_arst | Output | 1 | dest_clk | NA | Active |
src_arst asynchronous reset signal synchronized to destination clock domain. This output is registered. NOTE: Signal asserts asynchronously but deasserts synchronously to dest_clk. Width of the reset signal is at least (DEST_SYNC_FF*dest_clk) period. |
dest_clk | Input | 1 | NA | EDGE_RISING | Active | Destination clock. |
src_arst | Input | 1 | NA | NA | Active | Source asynchronous reset signal. |
Design Entry Method
Instantiation | Yes |
Inference | No |
IP and IP Integrator Catalog | No |
Available Attributes
Attribute | Type | Allowed Values | Default | Description |
---|---|---|---|---|
DEST_SYNC_FF | DECIMAL | 2 to 10 | 4 | Number of register stages used to synchronize signal in the destination clock domain. This parameter also determines the minimum width of the asserted reset signal. |
INIT_SYNC_FF | DECIMAL | 0, 1 | 0 |
0- Disable behavioral simulation initialization value(s) on synchronization registers. 1- Enable behavioral simulation initialization value(s) on synchronization registers. |
RST_ACTIVE_HIGH | DECIMAL | 0, 1 | 0 |
Defines the polarity of the asynchronous reset signal.
|
VHDL Instantiation Template
Library xpm;
use xpm.vcomponents.all;
-- xpm_cdc_async_rst: Asynchronous Reset Synchronizer
-- Xilinx Parameterized Macro, version 2022.1
xpm_cdc_async_rst_inst : xpm_cdc_async_rst
generic map (
DEST_SYNC_FF => 4, -- DECIMAL; range: 2-10
INIT_SYNC_FF => 0, -- DECIMAL; 0=disable simulation init values, 1=enable simulation init values
RST_ACTIVE_HIGH => 0 -- DECIMAL; 0=active low reset, 1=active high reset
)
port map (
dest_arst => dest_arst, -- 1-bit output: src_arst asynchronous reset signal synchronized to destination
-- clock domain. This output is registered. NOTE: Signal asserts asynchronously
-- but deasserts synchronously to dest_clk. Width of the reset signal is at least
-- (DEST_SYNC_FF*dest_clk) period.
dest_clk => dest_clk, -- 1-bit input: Destination clock.
src_arst => src_arst -- 1-bit input: Source asynchronous reset signal.
);
-- End of xpm_cdc_async_rst_inst instantiation
Verilog Instantiation Template
// xpm_cdc_async_rst: Asynchronous Reset Synchronizer
// Xilinx Parameterized Macro, version 2022.1
xpm_cdc_async_rst #(
.DEST_SYNC_FF(4), // DECIMAL; range: 2-10
.INIT_SYNC_FF(0), // DECIMAL; 0=disable simulation init values, 1=enable simulation init values
.RST_ACTIVE_HIGH(0) // DECIMAL; 0=active low reset, 1=active high reset
)
xpm_cdc_async_rst_inst (
.dest_arst(dest_arst), // 1-bit output: src_arst asynchronous reset signal synchronized to destination
// clock domain. This output is registered. NOTE: Signal asserts asynchronously
// but deasserts synchronously to dest_clk. Width of the reset signal is at least
// (DEST_SYNC_FF*dest_clk) period.
.dest_clk(dest_clk), // 1-bit input: Destination clock.
.src_arst(src_arst) // 1-bit input: Source asynchronous reset signal.
);
// End of xpm_cdc_async_rst_inst instantiation