Primitive: A Multi-Output high-fanout buffer for low-skew distribution of the PS Clock signals
- PRIMITIVE_GROUP: CLOCK
- PRIMITIVE_SUBGROUP: BUFFER
Introduction
A Multi-Output high-fanout buffer for low-skew distribution of the PS Clock signals.
Port Descriptions
Port | Direction | Width | Function |
---|---|---|---|
CLRB_LEAF | Input | 1 | Active low clear of BUFDIV_LEAF |
I | Input | 1 | Clock buffer input. |
O1 | Output | 1 |
|
O2 | Output | 1 |
|
O3 | Output | 1 |
|
O4 | Output | 1 |
|
Design Entry Method
Instantiation | Yes |
Inference | No |
IP and IP Integrator Catalog | Recommended |
Available Attributes
Attribute | Type | Allowed Values | Default | Description |
---|---|---|---|---|
MODE | STRING | "PERFORMANCE", "POWER" | "PERFORMANCE" |
Sets the mode of operation that determines the output clock generation.
For PERFORMANCE MODE, the outputs are generated as follows:
For POWER MODE, the outputs are generated as follows:
|
VHDL Instantiation Template
Unless they already exist, copy the following
two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- MBUFG_PS: A Multi-Output high-fanout buffer for low-skew distribution of the PS Clock signals
-- Versal Prime series
-- Xilinx HDL Language Template, version 2022.1
MBUFG_PS_inst : MBUFG_PS
generic map (
MODE => "PERFORMANCE" -- PERFORMANCE, POWER
)
port map (
O1 => O1, -- 1-bit output: Buffer
O2 => O2, -- 1-bit output: Buffer
O3 => O3, -- 1-bit output: Buffer
O4 => O4, -- 1-bit output: Buffer
CLRB_LEAF => CLRB_LEAF, -- 1-bit input: Active low clear
I => I -- 1-bit input: Clock buffer input
);
-- End of MBUFG_PS_inst instantiation
Verilog Instantiation Template
// MBUFG_PS: A Multi-Output high-fanout buffer for low-skew distribution of the PS Clock signals
// Versal Prime series
// Xilinx HDL Language Template, version 2022.1
MBUFG_PS #(
.MODE("PERFORMANCE") // PERFORMANCE, POWER
)
MBUFG_PS_inst (
.O1(O1), // 1-bit output: Buffer
.O2(O2), // 1-bit output: Buffer
.O3(O3), // 1-bit output: Buffer
.O4(O4), // 1-bit output: Buffer
.CLRB_LEAF(CLRB_LEAF), // 1-bit input: Active low clear
.I(I) // 1-bit input: Clock buffer input
);
// End of MBUFG_PS_inst instantiation
Related Information
- Versal ACAP Clocking Resources Architecture Manual (AM003)