Primitive: 5-input Dynamically Reconfigurable Look-Up Table (LUT)
- PRIMITIVE_GROUP: CLB
- PRIMITIVE_SUBGROUP: LUT
Introduction
This element is a runtime, dynamically reconfigurable, 5-input look-up table (LUT) that enables the changing of the logical function of the LUT during circuit operation. Using the CDI pin, a new INIT value can be synchronously shifted in serially to change the logical function. The O6 output pin produces the logical output function, based on the current INIT value loaded into the LUT and the currently selected I0-I4 input pins. Optionally, you can use the O5 output in combination with the O6 output to create two individual 4-input functions sharing the same inputs or a 5-input function and a 4-input function that uses a subset of the 5-input logic (see the following tables). This component occupies one of the eight LUT6 components within a SLICEM.
To cascade this element, connect the CDO pin from each element to the CDI input of the next element. This will allow a single serial chain of data (32-bits per LUT) to reconfigure multiple LUTs.
Port Descriptions
Port | Direction | Width | Function |
---|---|---|---|
CDI | Input | 1 | Reconfiguration data serial input. |
CDO | Output | 1 | Reconfiguration data cascaded output (optionally connect to the CDI input of a subsequent LUT). |
CE | Input | 1 | Active-High reconfiguration clock enable. |
CLK | Input | 1 | Reconfiguration clock. |
O5 | Output | 1 | 4-LUT output. |
O6 | Output | 1 | 5-LUT output. |
LUT Inputs: Logic inputs to the programmable look-up table. | |||
I0 | Input | 1 | Logic inputs to the programmable look-up table. |
I1 | Input | 1 | Logic inputs to the programmable look-up table. |
I2 | Input | 1 | Logic inputs to the programmable look-up table. |
I3 | Input | 1 | Logic inputs to the programmable look-up table. |
I4 | Input | 1 | Logic inputs to the programmable look-up table. |
Design Entry Method
Instantiation | Yes |
Inference | No |
IP and IP Integrator Catalog | No |
Available Attributes
Attribute | Type | Allowed Values | Default | Description |
---|---|---|---|---|
INIT | HEX | Any 32-bit HEX value | All zeroes | Specifies the initial logical expression of this element. |
IS_CLK_INVERTED | BINARY | 1'b0 to 1'b1 | 1'b0 | Indicates whether the CLK is active-High or active-Low. |
VHDL Instantiation Template
Library UNISIM;
use UNISIM.vcomponents.all;
-- CFGLUT5: 5-input Dynamically Reconfigurable Look-Up Table (LUT)
-- Versal Prime series
-- Xilinx HDL Language Template, version 2022.1
CFGLUT5_inst : CFGLUT5
generic map (
INIT => X"00000000", -- Initial logic function
IS_CLK_INVERTED => '0' -- Optional inversion for CLK
)
port map (
CDO => CDO, -- 1-bit output: Reconfiguration cascade
O5 => O5, -- 1-bit output: 4-LUT
O6 => O6, -- 1-bit output: 5-LUT
CDI => CDI, -- 1-bit input: Reconfiguration data
CE => CE, -- 1-bit input: Reconfiguration enable
CLK => CLK, -- 1-bit input: Clock
-- LUT Inputs inputs: Logic inputs
I0 => I0,
I1 => I1,
I2 => I2,
I3 => I3,
I4 => I4
);
-- End of CFGLUT5_inst instantiation
Verilog Instantiation Template
// CFGLUT5: 5-input Dynamically Reconfigurable Look-Up Table (LUT)
// Versal Prime series
// Xilinx HDL Language Template, version 2022.1
CFGLUT5 #(
.INIT(32'h00000000), // Initial logic function
.IS_CLK_INVERTED(1'b0) // Optional inversion for CLK
)
CFGLUT5_inst (
.CDO(CDO), // 1-bit output: Reconfiguration cascade
.O5(O5), // 1-bit output: 4-LUT
.O6(O6), // 1-bit output: 5-LUT
.CDI(CDI), // 1-bit input: Reconfiguration data
.CE(CE), // 1-bit input: Reconfiguration enable
.CLK(CLK), // 1-bit input: Clock
// LUT Inputs inputs: Logic inputs
.I0(I0),
.I1(I1),
.I2(I2),
.I3(I3),
.I4(I4)
);
// End of CFGLUT5_inst instantiation
Related Information
- Versal ACAP Configurable Logic Block Architecture Manual (AM005)