Primitive: 64-Deep by 8-bit Wide Multi Port Random Access Memory (Select RAM)
- PRIMITIVE_GROUP: CLB
- PRIMITIVE_SUBGROUP: LUTRAM
Introduction
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If the 7 inputs are all tied to the same data inputs, the RAM can become a 1 read/write port, 7 independent read port 64x1 octal port memory.
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If DIH is grounded, DOH is not used.
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If ADDRA through ADDRG are tied to the same address, the RAM becomes a 64x14 simple dual port RAM.
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If ADDRA through ADDRH are tied together, the RAM becomes a 64x16 single port RAM.
Port Descriptions
Port | Direction | Width | Function |
---|---|---|---|
DOA | Output | 1 | Read port data outputs addressed by ADDRA |
DOB | Output | 1 | Read port data outputs addressed by ADDRB |
DOC | Output | 1 | Read port data outputs addressed by ADDRC |
DOD | Output | 1 | Read port data outputs addressed by ADDRD |
DOE | Output | 1 | Read port data outputs addressed by ADDRE |
DOF | Output | 1 | Read port data outputs addressed by ADDRF |
DOG | Output | 1 | Read port data outputs addressed by ADDRG |
DOH | Output | 1 | Read/Write port data outputs addressed by ADDRH |
DIA | Input | 1 | Data write input addressed by ADDRH (read output is addressed by ADDRA) |
DIB | Input | 1 | Data write input addressed by ADDRH (read output is addressed by ADDRB) |
DIC | Input | 1 | Data write input addressed by ADDRH (read output is addressed by ADDRC) |
DID | Input | 1 | Data write input addressed by ADDRH (read output is addressed by ADDRD) |
DIE | Input | 1 | Data write input addressed by ADDRH (read output is addressed by ADDRE) |
DIF | Input | 1 | Data write input addressed by ADDRH (read output is addressed by ADDRF) |
DIG | Input | 1 | Data write input addressed by ADDRH (read output is addressed by ADDRG) |
DIH | Input | 1 | RAM 2-bit data write input addressed by ADDRH (read output is addressed by ADDRH) |
ADDRA | Input | 6 | Read port A address input |
ADDRB | Input | 6 | Read port B address input |
ADDRC | Input | 6 | Read port C address input |
ADDRD | Input | 6 | Read port D address input |
ADDRE | Input | 6 | Read port E address input |
ADDRF | Input | 6 | Read port F address input |
ADDRG | Input | 6 | Read port G address input |
ADDRH | Input | 6 | Read/write port H address input |
WE | Input | 1 | Write Enable |
WCLK | Input | 1 | Write clock (reads are asynchronous) |
Design Entry Method
Instantiation | Yes |
Inference | Recommended |
IP Catalog | No |
This element can be inferred by some synthesis tools by describing a RAM with a synchronous write and asynchronous read capability. Consult your synthesis tool documentation for details on RAM inference capabilities and coding examples. Xilinx suggests that you instantiate this component if you have a need to implicitly specify the RAM function, or if you need to manually place or relationally place the component.
If synchronous read capability is desired, the outputs can be connected to an FDRE/FDSE (FDCE/FDPE if asynchronous reset is needed) in order to improve the output timing of the function. However, this is not necessary for the proper operation of the RAM. If you want to have the data clocked on the negative edge of a clock, an inverter can be described on the clock input to this component. This inverter will be absorbed into the block during implementation and set as the IS_WCLK_INVERTED attribute giving the ability to write to the RAM on falling clock edges.
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Connect the WCLK input to the desired clock source
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Connect the DIA–DIH inputs to the data source to be stored
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Connect the DOA–DOH outputs to an FD* D input or other appropriate data destination, or leave unconnected if not used
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Connect the WE clock enable pin to the proper write enable source in the design
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Connect the ADDRH bus to the source for the read/write addressing
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Connect the ADDRA–ADDRG buses to the appropriate read address connections
The optional INIT_A–INIT_H attributes let you specify the initial memory contents of each port using a 64-bit hexadecimal value. The INIT value correlates to the RAM addressing by the following equation: ADDRy[z] = INIT_y[z]. For instance, if the RAM ADDRC port is addressed to 00001, then the INIT_C[1] values would be the initial values shown on the DOC port before the first write occurs at that address. If left unspecified, the initial contents will default to all zeros.
Available Attributes
Attribute | Type | Allowed Values | Default | Description |
---|---|---|---|---|
INIT_A | HEX | Any 128-bit value | All zeros | Specifies the initial contents of the RAM on port A. |
INIT_B | HEX | Any 128-bit value | All zeros | Specifies the initial contents of the RAM on port B. |
INIT_C | HEX | Any 128-bit value | All zeros | Specifies the initial contents of the RAM on port C. |
INIT_D | HEX | Any 128-bit value | All zeros | Specifies the initial contents of the RAM on port D. |
INIT_E | HEX | Any 128-bit value | All zeros | Specifies the initial contents of the RAM on port E. |
INIT_F | HEX | Any 128-bit value | All zeros | Specifies the initial contents of the RAM on port F. |
INIT_G | HEX | Any 128-bit value | All zeros | Specifies the initial contents of the RAM on port G. |
INIT_H | HEX | Any 128-bit value | All zeros | Specifies the initial contents of the RAM on port H. |
IS_WCLK_INVERTED | BINARY | 1'b0 to 1'b1 | 1'b0 | Specifies whether or not to use the optional inversion on the WCLK pin. |
VHDL Instantiation Template
Library UNISIM;
use UNISIM.vcomponents.all;
-- RAM64M8: 64-deep by 8-wide Multi Port LUT RAM
-- Versal Prime series
-- Xilinx HDL Language Template, version 2022.1
RAM64M8_inst : RAM64M8
generic map (
INIT_A => X"0000000000000000", -- Initial contents of A port
INIT_B => X"0000000000000000", -- Initial contents of B port
INIT_C => X"0000000000000000", -- Initial contents of C port
INIT_D => X"0000000000000000", -- Initial contents of D port
INIT_E => X"0000000000000000", -- Initial contents of E port
INIT_F => X"0000000000000000", -- Initial contents of F port
INIT_G => X"0000000000000000", -- Initial contents of G port
INIT_H => X"0000000000000000", -- Initial contents of H port
IS_WCLK_INVERTED => '0') -- Specifies active high/low WCLK
port map (
DOA => DOA, -- Read port A 1-bit output
DOB => DOB, -- Read port B 1-bit output
DOC => DOC, -- Read port C 1-bit output
DOD => DOD, -- Read port D 1-bit output
DOE => DOE, -- Read port E 1-bit output
DOF => DOF, -- Read port F 1-bit output
DOG => DOG, -- Read port G 1-bit output
DOH => DOH, -- Read/write port H 1-bit output
ADDRA => ADDRA, -- Read port A 6-bit address input
ADDRB => ADDRB, -- Read port B 6-bit address input
ADDRC => ADDRC, -- Read port C 6-bit address input
ADDRD => ADDRD, -- Read port D 6-bit address input
ADDRE => ADDRE, -- Read port E 6-bit address input
ADDRF => ADDRF, -- Read port F 6-bit address input
ADDRG => ADDRG, -- Read port G 6-bit address input
ADDRH => ADDRH, -- Read/write port H 6-bit address input
DIA => DIA, -- RAM 1-bit data write input addressed by ADDRD,
-- read addressed by ADDRA
DIB => DIB, -- RAM 1-bit data write input addressed by ADDRD,
-- read addressed by ADDRB
DIC => DIC, -- RAM 1-bit data write input addressed by ADDRD,
-- read addressed by ADDRC
DID => DID, -- RAM 1-bit data write input addressed by ADDRD,
-- read addressed by ADDRD
DIE => DIE, -- RAM 1-bit data write input addressed by ADDRE,
-- read addressed by ADDRE
DIF => DIF, -- RAM 1-bit data write input addressed by ADDRF,
-- read addressed by ADDRF
DIG => DIG, -- RAM 1-bit data write input addressed by ADDRG,
-- read addressed by ADDRG
DIH => DIH, -- RAM 1-bit data write input addressed by ADDRH,
-- read addressed by ADDRH
WCLK => WCLK, -- Write clock input
WE => WE -- Write enable input
);
-- End of RAM64M8_inst instantiation
Verilog Instantiation Template
// RAM64M8: 64-deep by 8-wide Multi Port LUT RAM (Mapped to eight LUT6s)
// Versal Prime series
// Xilinx HDL Language Template, version 2022.1
RAM64M8 #(
.INIT_A(64'h0000000000000000), // Initial contents of A Port
.INIT_B(64'h0000000000000000), // Initial contents of B Port
.INIT_C(64'h0000000000000000), // Initial contents of C Port
.INIT_D(64'h0000000000000000), // Initial contents of D Port
.INIT_E(64'h0000000000000000), // Initial contents of E Port
.INIT_F(64'h0000000000000000), // Initial contents of F Port
.INIT_G(64'h0000000000000000), // Initial contents of G Port
.INIT_H(64'h0000000000000000), // Initial contents of H Port
.IS_WCLK_INVERTED(1'b0) // Specifies active high/low WCLK
) RAM64M8_inst (
.DOA(DOA), // Read port A 1-bit output
.DOB(DOB), // Read port B 1-bit output
.DOC(DOC), // Read port C 1-bit output
.DOD(DOD), // Read port D 1-bit output
.DOE(DOE), // Read port E 1-bit output
.DOF(DOF), // Read port F 1-bit output
.DOG(DOG), // Read port G 1-bit output
.DOH(DOH), // Read/write port H 1-bit output
.DIA(DIA), // RAM 1-bit data write input addressed by ADDRD,
// read addressed by ADDRA
.DIB(DIB), // RAM 1-bit data write input addressed by ADDRD,
// read addressed by ADDRB
.DIC(DIC), // RAM 1-bit data write input addressed by ADDRD,
// read addressed by ADDRC
.DID(DID), // RAM 1-bit data write input addressed by ADDRD,
// read addressed by ADDRD
.DIE(DIE), // RAM 1-bit data write input addressed by ADDRD,
// read addressed by ADDRE
.DIF(DIF), // RAM 1-bit data write input addressed by ADDRD,
// read addressed by ADDRF
.DIG(DIG), // RAM 1-bit data write input addressed by ADDRD,
// read addressed by ADDRG
.DIH(DIH), // RAM 1-bit data write input addressed by ADDRD,
// read addressed by ADDRH
.ADDRA(ADDRA), // Read port A 6-bit address input
.ADDRB(ADDRB), // Read port B 6-bit address input
.ADDRC(ADDRC), // Read port C 6-bit address input
.ADDRD(ADDRD), // Read port D 6-bit address input
.ADDRE(ADDRE), // Read port E 6-bit address input
.ADDRF(ADDRF), // Read port F 6-bit address input
.ADDRG(ADDRG), // Read port G 6-bit address input
.ADDRH(ADDRH), // Read/write port H 6-bit address input
.WE(WE), // Write enable input
.WCLK(WCLK) // Write clock input
);
// End of RAM64M8_inst instantiation
Related Information
- Versal ACAP Configurable Logic Block Architecture Manual (AM005)