Classic SoC Boot Flow - 2022.1 English

Versal ACAP System Software Developers Guide (UG1304)

Document ID
Release Date
2022.1 English

The classic SoC boot is a solution that enables you to boot the processors in the scalar engines of the Versal ACAP and access the DDR memory before the programmable logic (PL) in the adaptable engines is configured. This allows DDR-based software like Linux or U-Boot to boot first followed by the PL, which can be configured later, if required, using any primary or secondary boot devices or through a DDR image store. The classic SoC boot feature is intended to treat the Versal ACAP boot sequences similar to the boot sequences for Zynq® UltraScale+™ MPSoCs. This solution is built using a dynamic function eXchange (DFX) flow through the Vivado IP integrator, which includes automatic floorplan generation and flow-specific design rule checks (DRCs). The entire PL is dynamic and can be completely reloaded while any operating system and DDR memory access remains active. A DFX flow is necessary when loading the PL after the initial PDI image load. The classic SoC boot is incompatible with the use of the CPM, including the PCIe controller and DMA features, and dynamic reconfiguration of sub-regions of the PL is not yet supported. For more details see the Versal ACAP Design Guide (UG1273). For information on DFX, see the Vivado Design Suite User Guide: Dynamic Function eXchange (UG909).

For more information on the classic SoC boot, including design requirements and a tutorial walk-through, see the classic SoC boot tutorial.