Programmable Logic - 2022.1 English

Versal ACAP System Software Developers Guide (UG1304)

Document ID
UG1304
Release Date
2022-04-21
Version
2022.1 English

You can use the Vivado IP integrator to configure the Versal ACAP programmable logic (PL). The PL is flexible, and the configuration uses building blocks or integrated components to create a customized design.

The PL is a complex structure that includes integrated and instantiated hardware accelerators, controllers, memories, and miscellaneous functional units.

  • Integrated functional units include a multi-gigabit Ethernet MAC.
  • Building blocks are used to instantiate functional units, and connect the integrated units to the interconnect and I/O structures. Building blocks include DSP, block RAM, UltraRAM, and clocking structures.
  • Instantiated functional units are built using the PL integrated building blocks and could include:
    Interconnects
    AXI, NoC interconnect
    Platform control components
    PS configuration and reset
    Digital functional units
    Adders, counters, floating point unit (FPU), and video
    Radio frequency-oriented (RF) functional units
    RF usage functional units, long term evolution (LTE), and radio