Additional Resources and Legal Notices - 2022.1 English

Versal ACAP System Software Developers Guide (UG1304)

Document ID: UG1304
Release Date: 2022-04-21
Version: 2022.1 English

Overview
Introduction to Versal ACAP
Navigating Content by Design Process
About This Guide
Programming View of Versal ACAP
Hardware Overview
Processing System
Application Processing Unit
Real-Time Processing Unit
Tightly Coupled Memory Interface
RPU Configuration Options
Programmable Logic
MicroBlaze Processors in the Programmable Logic
Development Tools
Vivado Design Suite
Vitis Software Platform
Accelerated Flow
Embedded Flow
Vitis Tools
PetaLinux Tools
Device Tree Generator
Open Source
Xilinx Arm GNU Tools
Linux Software Development Using Yocto
Yocto Project Development Environment
QEMU
AI Engine Development Environment
AI Engine Software Development Flow
AI Engine Runtime Stack
Software Stack
Bare-Metal Software Stack
The C Standard Library (libc)
The C Standard Library Mathematical Functions (libm)
Standalone BSP
Linux Software Stack
FreeRTOS Software Stack
Third-Party Software Stack
Software Development Flow
Bare-Metal Application Development in the Vitis Environment
Linux Application Development Using PetaLinux Tools
Linux Application Development Using the Vitis Software Platform
Software Design Paradigms
Frameworks for Multiprocessor Development
Symmetric Multiprocessing
Execution Domain and Images
Asymmetric Multiprocessing
OpenAMP
Virtualization with Hypervisor
Use of Hypervisors
Boot and Configuration
Versal ACAP Boot Process
Phase 1: Pre-Boot
Phase 2: Boot Setup
Phase 3: Boot and Configuration sequence by PLM (Platform Loader)
Phase 4: Post-Boot
Boot Flow
Non-Secure Boot Flow
Secure Boot Flow
PDI Content Integrity and Support for Secure Boot
Classic SoC Boot Flow
Boot Device Modes
Secondary Boot Process and Device Choices
Boot Process for Primary Boot Device
Fallback Boot and MultiBoot
Boot Mode Search Limits
Octal-SPI and Quad-SPI Boot Devices
SD/eMMC Boot Devices
SD/eMMC RAW Boot Mode
Programmable Device Image
Configuration Data Object
Creating a Boot Image (PDI)
Software Developer Control of PDI File Creation via BIF File
Methods for Programming the PDI to a Primary Boot Device
Platform Loader and Manager
PLM Boot and Configuration
BootROM, PLM Handoff State
PLM Subsystem
LPD Configuration
PL Configuration
FPD Configuration
DFX Configuration
CPM Configuration
Processor Subsystem Configuration
AI Engine Configuration
PLM Software Details
PLM Responsibilities
PLM Architecture
PLM Software
PLM Execution Flow
PLM Errors
PLM Major Error Codes
Exception Handling
PLM Event Logging
Logging PLM Terminal Prints
Logging Trace Events
Event Logging IPI Command
Event Logging Command Examples
Error Manager
Error Management Hardware
Error Management API Calls
Error Management CDO Commands
Error Events
PLM Interface (XilPLMI)
XilLoader
Image Store
XilLoader/IPI CDO Commands
Load Partial PDI
Load DDR Copy Image
Update Multiboot
Upgrade ImageStore
Deferred Image Loading
XilPM
XilSecure
XilSEM
PLM Usage
PLM Build Flags
PMC Memory Layout
Services Flow
Security
Security Features
Known Answer Tests
Secure Boot
Checksum Verification
Asymmetric Hardware Root-of-Trust (A-HWRoT) (Authentication Required)
RSA Engine
Elliptic Curve Cryptography Engine
Key Revocation
Encryption
DPA Counter Measure
Key Sources
Red Key
Black Key
User Key
Revocation
Symmetric Hardware Root-of-Trust (S-HWRoT) Boot Mode (Encryption Required)
True Random Number Generator
Versal ACAP Platform Management
Versal ACAP Platform Management Overview
Versal ACAP Power Domains
Versal DFX Management
Versal ACAP Platform Management Software Architecture
API Calls and Responses
Platform Management Communication Using IPIs
Platform Management Layers
Typical Platform Management API Call Flow
Requesting and Releasing Slave Nodes
Platform Management Default Subsystem
Activation of Subsystem
Using the API for Power Management
Implementing Power Management on a Processor Unit
Initializing the XilPM Library
Power Management Using XPm_InitFinalize
Working with Memory and Peripheral Devices
Requesting and Releasing a Node
Setting up Device Request Permissions
Requesting and Releasing a Device From a Standalone Application
AI Engine Clock Frequency Scaling
Changing Requirements
Self-Suspending
Setting a Wake-up Source
Resuming Execution
Suspend-Resume Flow
Suspending the Entire FPD Domain
Forcefully Powering Down the FPD
Using the API for Clock Management
Using the API for Reset Management
Using the API for Pin Management
Using Miscellaneous APIs
XPm_DevIoctl EEMI API
XPm_GetOpCharacteristic EEMI API
XPm_Query EEMI API
XPm_ActivateSubsystem API
Event Management Framework
Event Management in Standalone Application
Registering and Unregistering the Event Handler
Event Management in Linux Kernel
Registering and Unregistering the Event Handler
XilPM Client Implementation Details
Payload Mapping for API Calls to PMC
Payload Mapping for API Callbacks from the PMC
Issuing EEMI API Calls to the PMC
Handling API Callbacks from the PMC
PM Features in Linux
User Space Platform Management Interface
System Power States
Power Management for the CPU
CPU Hot-Plugging
CPU Idle
CPU Frequencies
Power Management for the Devices
Clock Gating
Run-time Power Management
Global General Storage Registers
Persistent Global General Storage Registers
Debug Interface
PM Linux Drivers
Trusted Firmware-A
Event Handling in TF-A
TF-A Application Binary Interface
Checking the API Version
Checking the Chip ID
Power State Coordination Interface
PS Management Controller Firmware
Relationship with PLM
General Flow of an EEMI API Call
Runtime Decoupling Using Version Control of the EEMI API
PSM Health Check in PLM
Target Development Platforms
Boards and Kits
Libraries
Additional Resources and Legal Notices
Xilinx Resources
Documentation Navigator and Design Hubs
References
Revision History
Please Read: Important Legal Notices

Back to home page