Optimize: Performance Analysis

Vitis Unified Software Platform Documentation: Embedded Software Development (UG1400)

Document ID
Release Date
2021.2 English

Performance analysis in the Vitis software platform provides functionality for viewing and analyzing different types of performance data. Its goal is to provide views, graphs, metrics, etc. to help extract useful information from the data, in a way that is more user-friendly and informative than huge text dumps.

Performance analysis provides the following features:

  • Support for viewing Arm data.
  • Support for viewing APM data with PS and MDM as master.
  • Support for viewing MicroBlaze data.
  • Support for viewing and analyzing live data.
  • Support for offline viewing of data.
  • Support for zooming out/in of the data.
  • Event filtering and searching.
  • Import and export of trace packages.

The Performance analysis feature in the Vitis software platform supports data collection from AXI Performance Monitor (APM) Event Counters, Arm Performance Monitor Unit (PMU) from a Zynq-7000 SoC processing system, and MicroBlaze performance monitoring counters. For an example usage of performance monitoring on a Zynq device, refer to System Performance Modeling. For a MicroBlaze design, APM can be used in a similar way as SPM.

To collect MicroBlaze performance data, the performance monitoring counters must be enabled in the Vivado hardware design. For more information, refer to the MicroBlaze Processor Reference Guide (UG984). The Vitis software platform monitors the following events for MicroBlaze processors:
  • Number of clock cycles
  • Any valid instruction executed
  • Read or write data request from/to data cache
  • Read or write data cache hit
  • Pipeline stalled
  • Instruction cache latency for memory read

The data is collected in the Vitis software platform in real time. The values from these counters are sampled every 10 ms. These values are used to calculate metrics shown in the Performance Counters view.

The Vitis software platform monitors the following PMU events for each Cortex-A9 CPU:

  • Data cache refill
  • Data cache access
  • Data stall
  • Write stall
  • Instruction rename
  • Branch miss

The following two Level-2 cache controller (L2C-PL330) counters are monitored:

  • Number of cache hits
  • Number of cache accesses

The following APM counters for each HP and ACP port are monitored:

  • Write Byte Count
  • Read Byte Count
  • Write Transaction Count
  • Total Write Latency
  • Read Transaction Count
  • Total Read Latency