Creating Standalone Software Design and Accessing Software Information - 2021.2 English

Vitis Unified Software Platform Documentation: Embedded Software Development (UG1400)
Document ID
UG1400
Release Date
2021-12-15
Version
2021.2 English

# List of the drivers in the software repository

hsi::get_sw_cores *uart*
uartlite_v2_01_a uartlite_v3_0 uartns550_v2_01_a
uartns550_v2_02_a uartns550_v3_0
uartns550_v3_1 uartps_v1_04_a uartps_v1_05_a uartps_v2_0
uartps_v2_1 uartps_v2_2

# Creates software design

hsi::create_sw_design swdesign -proc ps7_cortexa9_0 -os standalone
swdesign

# To switch to active software design

hsi::current_sw_design
swdesign

# Properties of the current software design

common::report_property [hsi::current_sw_design ]
Table 1. Example Table
Property Type Read-only Visible Value
APP_COMPILER string FALSE TRUE arm-xilinx-eabi-gcc
APP_COMPILER_FLAGS string FALSE TRUE  
APP_LINKER_FLAGS string FALSE TRUE  
BSS_MEMORY string FALSE TRUE  
CLASS string TRUE TRUE sw_design
CODE_MEMORY string FALSE TRUE  
DATA_MEMORY string FALSE TRUE  
NAME string TRUE TRUE swdesign

# The drivers associated to current hardware design

hsi::get_drivers
axi_bram_ctrl_0 axi_gpio_0 ps7_afi_0 ps7_afi_1 ps7_afi_2
ps7_afi_3 ps7_can_0
ps7_coresight_comp_0 ps7_ddr_0 ps7_ddrc_0 ps7_dev_cfg_0
ps7_dma_ns ps7_dma_s
ps7_ethernet_0 ps7_globaltimer_0 ps7_gpio_0 ps7_gpv_0
ps7_i2c_0 ps7_intc_dist_0
ps7_iop_bus_config_0 ps7_l2cachec_0 ps7_ocmc_0 ps7_pl310_0
ps7_pmu_0 ps7_qspi_0
ps7_qspi_linear_0 ps7_ram_0 ps7_ram_1 ps7_scuc_0
ps7_scugic_0 ps7_scutimer_0
ps7_scuwdt_0 ps7_sd_0 ps7_slcr_0 ps7_ttc_0 ps7_uart_1
ps7_usb_0 ps7_xadc_0
hsi% get_osstandalone

# Properties of the OS object

common::report_property[hsi::get_os]
Table 2. Example Table
Property Type Read-only Visible Value
CLASS string TRUE TRUE sw_proc
CONFIG.archiver string FALSE TRUE arm-xilinx-eabi-ar
CONFIG.compiler string FALSE TRUE arm-xilinx-eabi-gcc
CONFIG.compiler_flags string FALSE TRUE -O2 -c
CONFIG.extra_compiler_flags string FALSE TRUE -g
HW_INSTANCE string TRUE TRUE ps7_cortexa9_0
NAME string FALSE TRUE cpu_cortexa9
VERSION string FALSE TRUE 2.1

# Generate BSP. BSP source code will be dumped to the output directory.

hsi::generate_bsp -dir bsp_out

# List of available apps in the repository

hsi::generate_app -lapp
peripheral_tests dhrystone empty_application hello_world
lwip_echo_server
memory_tests rsa_auth_app srec_bootloader
xilkernel_thread_demo zynq_dram_test
zynq_fsbl linux_empty_app linux_hello_world
opencv_hello_world

# Generate template application

hsi::generate_app -app hello_world -proc ps7_cortexa9_0 -
dir app_out

# Generate Device Tree. Clone device tree repo from GIT to /device_tree_repository/device-treegenerator-master directory.

# Load the hardware design

hsi::open_hw_design zynq_1_wrapper.xsa

# Cloned GIT repo path

hsi::set_repo_path ./device_tree_repository/device-tree-generator-master

# Create sw design

hsi::create_sw_design sw1 -proc ps7_cortexa9_0 -os device_tree

# Generate device tree

hsi::generate_target {dts} -dir dtg_out