PMC Memory Layout - 2021.2 English

Versal ACAP System Software Developers Guide (UG1304)

Document ID
UG1304
Release Date
2021-10-27
Version
2021.2 English

This section contains the approximate details of the PMC memory layout and the PLM memory footprint, with the various PLM build options.

The following figure shows the PMC memory layout.

Figure 1. PMC Memory Layout

In the PLM, the PLM_DEBUG and PLM_PRINT_PERF build flags along with all modules, are enabled by default.