Phase 3: Boot and Configuration sequence by PLM (Platform Loader) - 2021.2 English

Versal ACAP System Software Developers Guide (UG1304)
Document ID
UG1304
Release Date
2021-10-27
Version
2021.2 English
Figure 1. Phase 3: Load Platform
9
The PPU begins to execute the PLM from the PPU RAM.
10
The PLM reads and processes the PDI components.
11
The PLM configures other parts of the Versal device using the PDI contents.
11a
The PLM applies the configuration data to the following Versal ACAP components:
  • PMC, PS blocks (CDO files)
    • Multiplexed I/Os (MIOs), clocks, resets, and etc.
  • NoC initialization and NPI components (NPI file)
    • DDR memory controller, NoC, GT, XPIPE, I/Os, clocking, and other NPI components
    • Adaptable Engine (PL) data (CFI file)
    • AI Engine configuration (AI Engine CDO)
      Note: The PMC triggers the scan clear of the individual programming control/status registers.
11b
The PLM loads the applications and data for the Arm® Cortex®-A72 and Cortex®-R5F processors to various memories specified by the ELF file. These memories include on-board DDR memory and internal memories, such as OCM and TCM.