Critical Pin Optimization performs remapping of logical LUT input pins to faster physical
pins to improve critical path timing. A critical path traversing a logical pin mapped to
a slow physical pin such as A1 or A2 is reassigned to a faster physical pin such as A6
or A5 if it improves timing. A cell with a LOCK_PINS property is skipped, and the cell
retains the mapping specified by LOCK_PINS. Logical-to-physical pin mapping is given by
the command get_site_pins.