To implement the synthesized design or netlist onto the targeted Xilinx® devices in Non-Project Mode, you must run the Tcl commands corresponding to the Implementation sub-processes:
- Opt Design (
opt_design) - Optimizes the logical design to make it easier to fit onto the target Xilinx device.
- Power Opt Design (
power_opt_design) (optional) - Optimizes design elements to reduce the power demands of the target Xilinx device.
- Place Design (
place_design) - Places the design onto the target Xilinx device and replicates logic to improve timing.
- Post-Place Power Opt Design (
power_opt_design) (optional) - Additional optimization to reduce power after placement.
- Post-Place Phys Opt Design (
phys_opt_design) (optional) - Optimizes logic and placement using estimated timing based on placement. Includes replication of high fanout drivers.
- Route Design (
route_design) - Routes the design onto the target Xilinx device.
- Post-Route Phys Opt Design (
phys_opt_design) (optional) - Optimizes logic, placement, and routing using actual routed delays.
- Write Bitstream (
write_bitstream) - Generates a bitstream for Xilinx device configuration except for Versal™ ACAP devices. Typically, bitstream generation follows implementation.
- Write Device Image (
write_device_image) - Generates a programmable device image for programming a Versal device.
For more information about writing the bitstream or creating a device image, see this link in the Vivado Design Suite User Guide: Programming and Debugging (UG908).
These steps are collectively known as implementation. Enter the commands in any of the following ways:
- In the Tcl Console from the Vivado® IDE.
- From the Tcl prompt in the Vivado Design Suite Tcl shell.
- Using a Tcl script with the implementation commands and source the script in the Vivado Design Suite.