- Explore
- Higher placer effort in detail placement and post-placement
optimization.
- WLDrivenBlockPlacement
- Wirelength-driven placement of RAM and DSP blocks. Override timing-driven
placement by directing the Placer to minimize the distance of connections to
and from blocks. This directive can improve timing to and from RAM and DSP
blocks.
- EarlyBlockPlacement
- Timing-driven placement of RAM and DSP blocks. The RAM and DSP block
locations are finalized early in the placement process and are used as
anchors to place the remaining logic.
- ExtraNetDelay_high
- Increases estimated delay of high fanout and long-distance nets. This
directive can improve timing of critical paths that meet timing after
place_design but fail timing in route_design due to overly optimistic
estimated delays. Two levels of pessimism are supported: high and low.
ExtraNetDelay_high applies the highest level of pessimism.
- ExtraNetDelay_low
- Increases estimated delay of high fanout and long-distance nets. This
directive can improve timing of critical paths that have met timing after
place_design but fail timing in
route_design due to overly optimistic estimated delays.
Two levels of pessimism are supported: high and low. ExtraNetDelay_low
applies the lowest level of pessimism.
- SSI_SpreadLogic_high
- Spreads logic throughout the SSI device to avoid creating congested regions.
Two levels are supported: high and low. SpreadLogic_high achieves the
highest level of spreading.
- SSI_SpreadLogic_low
- Spreads logic throughout the SSI device to avoid creating congested regions.
Two levels are supported: high and low. SpreadLogic_low achieves a minimal
level of spreading.
- AltSpreadLogic_high
- Spreads logic throughout the device to avoid creating congested regions.
Three levels are supported: high, medium, and low. AltSpreadLogic_high
achieves the highest level of spreading.
- AltSpreadLogic_medium
- Spreads logic throughout the device to avoid creating congested regions.
Three levels are supported: high, medium, and low. AltSpreadLogic_medium
achieves a nominal level of spreading.
- AltSpreadLogic_low
- Spreads logic throughout the device to avoid creating congested regions.
Three levels are supported: high, medium, and low. AltSpreadLogic_low
achieves a minimal level of spreading.
- ExtraPostPlacementOpt
- Higher placer effort in post-placement optimization.
- ExtraTimingOpt
- Use an alternate set of algorithms for timing-driven placement during the
later stages.
- SSI_SpreadSLLs
- Partition across SLRs and allocate extra area for regions of higher
connectivity.
- SSI_BalanceSLLs
- Partition across SLRs while attempting to balance SLLs between SLRs.
- SSI_BalanceSLRs
- Partition across SLRs to balance number of cells between SLRs.
- SSI_HighUtilSLRs
- Force the placer to attempt to place logic closer together in each SLR.
- RuntimeOptimized
- Run fewest iterations, trade higher design performance for faster run
time.
- Quick
- Absolute, fastest run time, non-timing-driven, performs the minimum required
for a legal design.
- Default
- Run place_design with default settings.