Viewing SSN Results - 2020.2 English

After the analysis is complete, the Noise window opens.

Click the links on the left side of the window to view different information about the SSN analysis. For example, click I/O Bank Details to view the following information:

Name

Displays the I/O banks available in the device. Each I/O bank has pin icons indicating how full the bank is. A check mark indicates a passing result, and a red circle indicates a failure.

Port

Displays the name of the user I/O in the FPGA design.

I/O Std, V_CCO, Slew, Drive Strength

Displays the appropriate values for the port or bank.

Off-Chip Termination

Displays the default terminations for each I/O standard, if one exists. Displays either None or a short description of the expected or defined off-chip termination style. For example, FP_VTT_50 describes a far-end parallel 50 Ω termination to VTT termination style. HSTL_1 describes a far-end 40 Ω termination to VTT. The full list of termination styles is available in one of the following user guides, depending on your device.

• 7 Series FPGAs SelectIO Resources User Guide (UG471)
• UltraScale Architecture SelectIO Resources User Guide (UG571)

For LVTTL (at 2 mA, 4 mA, 6 mA, and 8 mA) no termination is assumed. However, for LVTTL (at 12 mA and 16 mA) a far-end parallel termination of 50Ω to VTT is assumed. As a result of this termination, the available noise margin is less for signals with drive strength of 12 mA, or more, when compared to 2 mA to 8 mA. 7 series devices, Zynq®-7000, and UltraScale™ devices use this assumption for applicable drive strengths.

To change the settings, use either of the following methods:

• Use the CSV file import feature described in Importing a CSV File.
• In the I/O Ports table, select an item from the drop-down list.

Remaining Margin %

Displays the amount of noise margin that is left over after accounting for all SSN in the bank.

Notes

Displays information about the I/O bank or groups.