SSN Analysis - 2020.2 English

Vivado Design Suite User Guide: I/O and Clock Planning (UG899)
Document ID
UG899
Release Date
2021-03-09
Version
2020.2 English
To generate an estimate of potential noise disruptions, run SSN analysis as described in Working with SSN Analysis. Xilinx recommends that you address noise-related issues before starting board planning. For more information, see the SelectIO™ resources for your device:
  • 7 Series FPGAs SelectIO Resources User Guide (UG471)
  • UltraScale Architecture SelectIO Resources User Guide (UG571)
and the Memory Resources resources for your device:
  • UltraScale Architecture Memory Resources User Guide (UG573)
  • Zynq-7000 SoC and 7 series Devices Memory Interface Solutions (UG586)