Copying I/O Port Assignments Between Designs - 2020.2 English

Vivado Design Suite User Guide: I/O and Clock Planning (UG899)
Document ID
UG899
Release Date
2021-03-09
Version
2020.2 English
You can create a scoped XDC file to copy UltraScale architecture Memory IP I/O constraints from one design to another. This is useful if you want to:
  • Perform memory I/O assignments in an IP example design and then copy the assignments to your design.
  • Create an example design containing the Memory IP and related I/O assignments from your design.
Note: Because top-level port names might differ between the designs, you must use a scoped XDC file to copy the constraints.

To create a scoped XDC file to copy Memory IP I/O constraints:

  1. Open the elaborated or synthesized design to copy the I/O assignments from.
  2. In the Tcl Console, enter the following command to write a scoped XDC file for the Memory IP I/O constraints:
    write_xdc -cell <memory_ip_instance_name> -file <output file name>
  3. Open the elaborated or synthesized design to copy the I/O assignments to.
  4. In the Tcl Console, enter the following command to read the scoped XDC file for the Memory IP I/O constraints:
    read_xdc -cell <memory_ip_instance_name> -file <output file name>
  5. Select File > Constraints > Save to interpret the I/O constraints to the top-level ports and write the constraints into the target constraint file.
    Note: The Tcl command equivalent is: save_constraints