UltraScale Architecture Memory IP I/O Planning in the Elaborated Design - 2020.2 English

Vivado Design Suite User Guide: I/O and Clock Planning (UG899)
Document ID
UG899
Release Date
2021-03-09
Version
2020.2 English

When using the elaborated design for memory I/O planning, you must set the proper Elaboration options before opening the design as follows:

  1. In the Vivado IDE, select Flow > Elaboration Settings.
  2. In the Project Settings dialog box, ensure that the Netlist model and Load constraints options are selected.

Loading the netlist model allows the elaborated design to read the synthesized Memory IP with the selected I/O properties, such as IOSTANDARD and OUTPUT_IMPEDANCE. If you use the black box model, you cannot do Memory IP I/O planning in the elaborated design.