Automatically Inferring I/O Port Interfaces - 2020.2 English

Vivado Design Suite User Guide: I/O and Clock Planning (UG899)

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2020.2 English
Recommended: If your project targets a platform board rather than a part, Xilinx recommends that you use the Vivado Design Suite platform board flow to configure and apply board pinout constraints using the Board tab in the Customize IP dialog box or in the Board window in the Vivado IP integrator. For more information on the platform board flow, see this link in the Vivado Design Suite User Guide: System-Level Design Entry (UG895).

You can view the interfaces that are connected from an IP to the top-level ports of your design. For these IP interfaces, the Vivado tools automatically infer a pin planning interface that groups the related top-level I/O ports. This provides a symbolic way of referring to the interface in the context of the top-level design. For example, in the following figure, the led_8bits_tri_o bus is a general purpose I/O (GPIO) interface that is grouped under the GPIO_9847 pin planning interface.

You can view the board part pins associated with the I/O ports from the Board Part Pin column in the I/O Ports window. In the following figure, the ports associated with pin-planning interface GPIO_9847 are constrained to board part pins led_8bits_tri_o[7:0].

Note: The number 9847 in GPIO_9847 is used for unique identification of the GPIO interface when there are multiple GPIO interfaces in the design. There is no specific meaning for the number.
Figure 1. Automatic Inference of I/O Port Interfaces