Using the Settings Panel - 2020.2 English

Xilinx Power Estimator User Guide (UG440)

Document ID
Release Date
2020.2 English

Use the Settings panel to specify details of the device, board, cooling and ISE or Vivado® Design Suite settings. This panel varies slightly depending on the targeted device. A Kintex UltraScale device example is presented in the following figure.

Some settings are dependent on other settings. When this occurs the dependent cell becomes un-editable and turns to a gray background.

Figure 1. Settings Panel

The sections in the Settings panel are:

Select the smallest device which meets your requirements.
Important: Larger devices exhibit higher device static power consumption.
The 7 series spreadsheet has a Voltage ID Used entry, which applies to Virtex®-7, -1 Speed Grade, Commercial Temp Grade, and Maximum Process FPGAs only. If Voltage ID Used is set to Yes, XPE will perform all of its power calculations based on the device operating at the Voltage ID voltage. The Voltage ID (VID) voltage is the minimum possible VCCINT voltage at which the Xilinx® device can run and still meet its performance specifications. This voltage is tested when the Xilinx device is manufactured and the value is programmed into the DNA eFuse register on the Xilinx device. Activating the VID feature in your design to operate the Xilinx device at this VID voltage can result in a significant power savings over operating the Xilinx device at its nominal voltage.
For XPE to report the estimated junction temperature it needs to understand how the device logic is configured and activated. It also needs a description of the device environment. The information of how heat can be transferred into the surrounding air (ΘSA) or PCB (ΘJB) affects the device junction temperature. If these parameters are known enter them; otherwise, select from the different drop-down menus the environment settings closest to your specific project. This will help to indirectly determine Effective ΘJA.
Important: XPE uses a 2-R thermal model to calculate the junction temperature. The XPE thermal model assumes two main paths of heat flow through the top and bottom of the device into the board. The thermal model uses environment settings entered for ambient temperature, airflow, heat sink, and board selection in the effective thermal resistance and junction temperature calculations.

Because the junction temperature estimate in XPE is based on a board setup that might vary from your actual board setup, it might not account for the effect of other heat sources on the actual board system, such as other board components close to the Xilinx device. These variations can result in differences between the XPE thermal estimate and a thermal measurement of the actual system.

The Implementation options are labeled as per the selected device. The labels are as follows:
  • Implementation (7 series, UltraScale™ and UltraScale+™ devices)
  • PL Implementation ( Zynq®-7000 SoC and Zynq® UltraScale+™ MPSoCs)
  • ISE (earlier device architectures)

Settings in this section are available to focus the synthesis and implementation tools on minimizing towards different objectives. Adjust this area to best match the ISE or Vivado Design Suite settings you plan on using. This option affects the core dynamic power by an amount seen in a suite of customer designs.

Important: In an UltraScale/UltraScale+ device spreadsheet, this section is labeled Implementation, and only Power Optimization, Default and None settings are available. In a 7 series spreadsheet, this section is labeled Implementation, and only Default and Power Optimization settings are available. In a Zynq-7000 SoC and Zynq UltraScale+ MPSoC spreadsheets, this section is labeled PL Implementation, and only Default, Power Optimization, and Powered Off settings are available.

Optimization settings are:

Area Reduction
Minimizes slice usage
Default ISE Design Suite options
Default ISE or Vivado Design Suite options
Minimum Run-time
Minimizes the run-time
Power Optimization
Minimizes core dynamic power
Timing Performance
Verifies the timing performance
Powered Off
Zynq-7000 SoC and Zynq UltraScale+ MPSoC devices only
None (UltraScale/UltraScale+ devices only)
Turns off all power optimizations
Power Mode
Power Mode is available for some device families. This setting allows you to review the estimated power for the different active and power down modes of the device.