Clock Source for Quad-based PLL - 2020.2 English

Xilinx Power Estimator User Guide (UG440)

Document ID
Release Date
2020.2 English

For UltraScale and UltraScale+ devices, there are two Quad based Phase Locked Loops (QPLL0 and QPLL1) for jitter performance or Channel based ring oscillator Phase Locked Loop (CPLL). You can select QPLL0 that runs at 16 GHz with an output divider of 2 as a clock source which is more conservative. For example: 16.375 Gb/s/2 =8.1875 Gb/s. You can also select QPLL1 running at 8 GHz. For example, 8.1875 Gb/s.