Step 1: Configuring and Running the Timing Simulation using Vivado Simulator - 2024.1 English

Vivado Design Suite Tutorial: Power Analysis and Optimization (UG997)

Document ID
UG997
Release Date
2024-05-30
Version
2024.1 English
  1. In the Implementation Complete dialog box, select Open Implemented Design and click OK to open the implemented design. When prompted to save the project before opening an implemented design, click Don’t Save.

    Now you are ready to set up and launch the Vivado simulator to run post implementation timing simulation. Set the timing simulation properties in Vivado IDE, and run the timing simulation.

  2. In the Flow Navigator, click Settings and select Simulation to set the timing simulation properties. In the Settings dialog box, the following defaults are automatically set:
    • Simulation set: sim_1
    • Simulation top-module name: testbench
  3. In the Elaboration tab, make sure that debug_level is set to typical, which is the default value.
  4. In the Simulation tab, set the SAIF file name xsim.simulate.saif to power_tutorial_timing_xsim.saif.
  5. Set the xsim.simulate.saif_scope to testbench/dut_fpga.
  6. Observe that the simulation run time xsim.simulate.runtime is 1000 ns.
  7. Check xsim.simulate.log_all_signals.
  8. Click OK.

    With the simulation settings properly configured, you can launch the Vivado simulator to perform a timing simulation of the post implemented design.

  9. In the Flow Navigator, click Run Simulation > Run Post-Implementation Timing Simulation.

  10. After the Vivado simulator finishes simulating the design, ensure that the requested SAIF file is generated. Check to see that the requested SAIF file in the simulation settings prior to running simulation appears in this directory:
    <project_directory>/power_tutorial1/power_tutorial1.sim/ sim_1/impl/timing/power_tutorial_timing_xsim.saif